A Fully Integrated Mixed-Signal Compute-In-Memory Accelerator for Solving Arbitrary Order Boolean Satisfiability Problems

This paper presents a mixed-signal In-Memory Computing (IMC) accelerator with 256 \times 128 10T bi-directional SRAM array in 55 nm CMOS process, for solving arbitrary-order KBoolean Satisfiability (K-SAT) problems. It achieves nearly an order of magnitude faster solution times compared to other sin...

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Veröffentlicht in:Digest of technical papers - Symposium on VLSI Technology S. 1 - 3
Hauptverfasser: Bhattacharya, Tinish, Kwon, Dongseok, Hutchinson, George Higgins, Zhang, Xiangyi, Rozada, Ignacio, Strukov, Dmitri
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: JSAP 08.06.2025
Schlagworte:
Bidirectional control
CMOS process
Cryptography
In-memory computing
Random access memory
Very large scale integration
ISSN:2158-9682
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Zusammenfassung:This paper presents a mixed-signal In-Memory Computing (IMC) accelerator with 256 \times 128 10T bi-directional SRAM array in 55 nm CMOS process, for solving arbitrary-order KBoolean Satisfiability (K-SAT) problems. It achieves nearly an order of magnitude faster solution times compared to other single-variable update ASIC solvers on uniform random 3-SAT problems, while outperforming all other solvers by 10 \div 200 \times on the studied higher-order K-SAT problems, relevant to cryptography applications.
ISSN:2158-9682
DOI:10.23919/VLSITechnologyandCir65189.2025.11074791