Modeling and Analysis Technique for the Formal Verification of System-on-Chip Address Maps: Extended Abstract

This paper proposes a modeling and analysis technique to verify SoC address maps. The approach involves (i) modeling the specification and implementation address map using a unified graph model, and (ii) analysis of equivalence in terms of address maps between two such models. Using a state-of-the-a...

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Veröffentlicht in:Proceedings - Design, Automation, and Test in Europe Conference and Exhibition S. 1 - 2
Hauptverfasser: Mook, Niels, De Kock, Erwin, Arts, Bas, Chakraborty, Soham, Van Deursen, Arie
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: EDAA 31.03.2025
Schlagworte:
Analytical models
Europe
Formal verification
System-on-chip
ISSN:1558-1101
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Zusammenfassung:This paper proposes a modeling and analysis technique to verify SoC address maps. The approach involves (i) modeling the specification and implementation address map using a unified graph model, and (ii) analysis of equivalence in terms of address maps between two such models. Using a state-of-the-art mid-size SoC design, we demonstrate the proposed solution is able to analyze and verify address maps of complex SoC designs and to identify the causes of discrepancies.
ISSN:1558-1101
DOI:10.23919/DATE64628.2025.10993069