Modeling and Analysis Technique for the Formal Verification of System-on-Chip Address Maps: Extended Abstract

This paper proposes a modeling and analysis technique to verify SoC address maps. The approach involves (i) modeling the specification and implementation address map using a unified graph model, and (ii) analysis of equivalence in terms of address maps between two such models. Using a state-of-the-a...

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Bibliographic Details

Published in:	Proceedings - Design, Automation, and Test in Europe Conference and Exhibition pp. 1 - 2
Main Authors:	Mook, Niels, De Kock, Erwin, Arts, Bas, Chakraborty, Soham, Van Deursen, Arie
Format:	Conference Proceeding
Language:	English
Published:	EDAA 31.03.2025
Subjects:	Analytical models Europe Formal verification System-on-chip
ISSN:	1558-1101
Online Access:	Get full text
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