Modeling and Analysis Technique for the Formal Verification of System-on-Chip Address Maps: Extended Abstract - Mook, Niels; De Kock, Erwin; Arts, Bas; Chakraborty, Soham; Van Deursen, Arie (Proceedings - Design, Automation, and Test in Europe Conference and Exhibition, 2025)
This paper proposes a modeling and analysis technique to verify SoC address maps. The approach involves (i) modeling the specification and implementation address map using a unified graph model, and (ii) analysis of equivalence in terms of address maps between two such models. Using a state-of-the-art mid-size SoC design, we demonstrate the proposed solution is able to analyze and verify address maps of complex SoC designs and to identify the causes of discrepancies.