High-Performance Computing with FPGA-Based Parallel Data Processing Systems

Traditional architectures of Central Processing Units (CPUs) and Graphics Processing Units (GPUs) are becoming unsuitable for High-Performance Computing (HPC) due to their high-power consumption and inability to process data in real-time. This study proposes a novel parallel data processing system t...

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Veröffentlicht in:	2024 International Conference on Sustainable Communication Networks and Application (ICSCNA) S. 294 - 300
Hauptverfasser:	Vaithianathan, Muthukumaran, Udkar, Shivakumar, Roy, Deepanjan, Reddy, Manjunath, Rajasekaran, Senkadir
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 11.12.2024
Schlagworte:	Computer architecture Dynamic scheduling Field programmable gate arrays Field Programming Gate Array (FPGA) High performance computing High-Performance Computing (HPC) Low Latency Modular Architecture Parallel Data Processing Parallel processing Pipelines Processor scheduling Real-time systems Scalability Throughput
Online-Zugang:	Volltext
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