High-Performance Computing with FPGA-Based Parallel Data Processing Systems
Traditional architectures of Central Processing Units (CPUs) and Graphics Processing Units (GPUs) are becoming unsuitable for High-Performance Computing (HPC) due to their high-power consumption and inability to process data in real-time. This study proposes a novel parallel data processing system t...
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| Vydáno v: | 2024 International Conference on Sustainable Communication Networks and Application (ICSCNA) s. 294 - 300 |
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11.12.2024
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| Abstract | Traditional architectures of Central Processing Units (CPUs) and Graphics Processing Units (GPUs) are becoming unsuitable for High-Performance Computing (HPC) due to their high-power consumption and inability to process data in real-time. This study proposes a novel parallel data processing system that is based on FPGAs and capitalizes on the remarkable reconfigurability of FPGAs to enhance the speed and efficiency of computation. The system's modular architecture combines pipeline parallelism with dataflow computation, enabling the continuous and concurrent execution of tasks with a substantially reduced latency. Throughput and scalability are enhanced by dynamic task scheduling, enhanced resource allocation, hardware-accelerated compute cores, and other critical features. The proposed FPGA-based system boasts a throughput that is up to five times greater, a latency that is 60% lower, and a power consumption that is 40% lower than conventional architectures based on CPUs and GPUs, as evidenced by the results of their experiments. |
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| AbstractList | Traditional architectures of Central Processing Units (CPUs) and Graphics Processing Units (GPUs) are becoming unsuitable for High-Performance Computing (HPC) due to their high-power consumption and inability to process data in real-time. This study proposes a novel parallel data processing system that is based on FPGAs and capitalizes on the remarkable reconfigurability of FPGAs to enhance the speed and efficiency of computation. The system's modular architecture combines pipeline parallelism with dataflow computation, enabling the continuous and concurrent execution of tasks with a substantially reduced latency. Throughput and scalability are enhanced by dynamic task scheduling, enhanced resource allocation, hardware-accelerated compute cores, and other critical features. The proposed FPGA-based system boasts a throughput that is up to five times greater, a latency that is 60% lower, and a power consumption that is 40% lower than conventional architectures based on CPUs and GPUs, as evidenced by the results of their experiments. |
| Author | Reddy, Manjunath Vaithianathan, Muthukumaran Udkar, Shivakumar Rajasekaran, Senkadir Roy, Deepanjan |
| Author_xml | – sequence: 1 givenname: Muthukumaran surname: Vaithianathan fullname: Vaithianathan, Muthukumaran email: muthu.v@samsung.com organization: Samsung Semiconductor Inc.,San Diego,USA – sequence: 2 givenname: Shivakumar surname: Udkar fullname: Udkar, Shivakumar email: udkar.shiv@gmail.com organization: AMD Inc.,Colorado,USA – sequence: 3 givenname: Deepanjan surname: Roy fullname: Roy, Deepanjan email: mail.droy03@gmail.com organization: NVIDIA Corporation Inc.,Texas,USA – sequence: 4 givenname: Manjunath surname: Reddy fullname: Reddy, Manjunath email: reddym@qualcomm.com organization: Qualcomm Inc.,San Diego,USA – sequence: 5 givenname: Senkadir surname: Rajasekaran fullname: Rajasekaran, Senkadir email: senkadir.r@samsung.com organization: Samsung Semiconductor Inc.,San Diego,USA |
| BookMark | eNo1j8tOwzAUBY0ECyj9AxbmAxLs2HHiZQj0ISqI1O6rG-e6tZRHZRuh_j1UwOosZjTSuSPX4zQiIY-cpZwz_bSut_V7pUTBZZqxTKaclUpmml2RuS50KQTPBWNc3JK3lTsckwa9nfwAo0FaT8PpM7rxQL9cPNJFs6ySZwjY0QY89D329AUi0MZPBkO4iNtziDiEe3JjoQ84_9sZ2S1ed_Uq2Xws13W1SZzmMTGlyjFTppDQlQxBF9JK0VqrOi6tabVgtmit-AG5Lk1nDGt1x0HqVhtlQczIw2_WIeL-5N0A_rz_vyi-ATeLTOM |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IL CBEJK RIE RIL |
| DOI | 10.1109/ICSCNA63714.2024.10864290 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Xplore POP ALL IEEE Xplore All Conference Proceedings IEEE Xplore IEEE Proceedings Order Plans (POP All) 1998-Present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| EISBN | 9798331530013 |
| EndPage | 300 |
| ExternalDocumentID | 10864290 |
| Genre | orig-research |
| GroupedDBID | 6IE 6IL CBEJK RIE RIL |
| ID | FETCH-LOGICAL-i91t-c865e26c74ad80ea974f43bff6d14fcb930f7bf3a97598cdcc0b9d1a49b9c6fa3 |
| IEDL.DBID | RIE |
| IngestDate | Wed Feb 19 06:11:51 EST 2025 |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-i91t-c865e26c74ad80ea974f43bff6d14fcb930f7bf3a97598cdcc0b9d1a49b9c6fa3 |
| PageCount | 7 |
| ParticipantIDs | ieee_primary_10864290 |
| PublicationCentury | 2000 |
| PublicationDate | 2024-Dec.-11 |
| PublicationDateYYYYMMDD | 2024-12-11 |
| PublicationDate_xml | – month: 12 year: 2024 text: 2024-Dec.-11 day: 11 |
| PublicationDecade | 2020 |
| PublicationTitle | 2024 International Conference on Sustainable Communication Networks and Application (ICSCNA) |
| PublicationTitleAbbrev | ICSCNA |
| PublicationYear | 2024 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| Score | 1.8921052 |
| Snippet | Traditional architectures of Central Processing Units (CPUs) and Graphics Processing Units (GPUs) are becoming unsuitable for High-Performance Computing (HPC)... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 294 |
| SubjectTerms | Computer architecture Dynamic scheduling Field programmable gate arrays Field Programming Gate Array (FPGA) High performance computing High-Performance Computing (HPC) Low Latency Modular Architecture Parallel Data Processing Parallel processing Pipelines Processor scheduling Real-time systems Scalability Throughput |
| Title | High-Performance Computing with FPGA-Based Parallel Data Processing Systems |
| URI | https://ieeexplore.ieee.org/document/10864290 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NSwMxEA1aRDypWPGbCF7T7jbZfBxrtSpCWbCH3koymUBBWqlbf7_Jdmvx4MFbSB4EJpDJTObNI-QOjVTotWE5FpKJIIok5O4Ylzq4HAoE5WuxCTUa6cnElA1ZvebCIGJdfIadNKz_8v0CVilV1k2qQPH-jBH6rlJyTdbaJ7dN38zuy-BtMOrL1IMuBn490dngfymn1I5jePjPLY9Ie0vBo-WPczkmOzg_Ia-pKoOV21p_uhZliAiaEqp0WD712X10TJ6WdplkUt7pg60sbfgACdj0KG-T8fBxPHhmjRoCm5m8YqBlgT0JSlivM7QxDgiCuxCkz0UAZ3gWlAs8LhRGgwfInPG5FcYZkMHyU9KaL-Z4RqiSXhYCIeM8BkNCaq8BfHz5uCxBwzlpJ0NMP9b9LqYbG1z8MX9JDpK5U5FHnl-RVrVc4TXZg69q9rm8qU_pG1OWlXE |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LSwMxEA5SRT2pWPFtBK9pN81jk2Ot1pbWZcEeeit5QkG2Urf-fpPt1uLBg7eQTAhMIJNJvm8-AB6c5KmzQiLsGEfUUxaF3DUiXHiNDXMmtZXYRJplYjqVeU1Wr7gwzrkKfOZasVn95duFWcWnsnZUBQrnZ8jQdxmlnWRN19oH93XlzPaw99bLujxWoQupX4e2NjN-aadUoaN_9M9Fj0FzS8KD-U94OQE7rjgFo4jLQPkW7Q_XsgzBAsYnVdjPX7roMYQmC3O1jEIp7_BJlQrWjIBoWFcpb4JJ_3nSG6BaDwHNJS6REZy5DjcpVVYkToVMwFOivecWU2-0JIlPtSdhgElhrDGJlhYrKrU03CtyBhrFonDnAKbcckadSQgJ6RDlwgpjbLj76CSa-gvQjI6YfawrXsw2Prj8o_8OHAwmr-PZeJiNrsBhdH2EfGB8DRrlcuVuwJ75Kuefy9tqx74BSYqYuA |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2024+International+Conference+on+Sustainable+Communication+Networks+and+Application+%28ICSCNA%29&rft.atitle=High-Performance+Computing+with+FPGA-Based+Parallel+Data+Processing+Systems&rft.au=Vaithianathan%2C+Muthukumaran&rft.au=Udkar%2C+Shivakumar&rft.au=Roy%2C+Deepanjan&rft.au=Reddy%2C+Manjunath&rft.date=2024-12-11&rft.pub=IEEE&rft.spage=294&rft.epage=300&rft_id=info:doi/10.1109%2FICSCNA63714.2024.10864290&rft.externalDocID=10864290 |