Bilinear Interpolation Algorithm Based on Verilog

This paper investigates a Verilog-based implementation of a bilinear interpolation algorithm aimed at solving the problem of pixel computation during image enlargement. The bilinear interpolation algorithm, as an effective image processing method, has a wide range of applications in the fields of im...

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Vydané v:IEEE International Conference on Electronic Information and Communication Technology (Online) s. 1375 - 1379
Hlavní autori: Lu, Yao, Yang, Xiaoling, Jin, Yongbo
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 31.07.2024
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ISSN:2836-7782
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Abstract This paper investigates a Verilog-based implementation of a bilinear interpolation algorithm aimed at solving the problem of pixel computation during image enlargement. The bilinear interpolation algorithm, as an effective image processing method, has a wide range of applications in the fields of image processing and computer vision. This algorithm is implemented through the Verilog programming language and includes key steps such as pixel coordinate conversion, nearest neighbor finding, and linear interpolation operations. On hardware platforms such as FPGAs, the use of fixed-point design optimizes the use of resources, improves computational efficiency, and meets real-time requirements. The correctness and effectiveness of the algorithm are verified through simulation tests. This algorithm implementation is characterized by high accuracy and speed and is suitable for real-time image processing applications. This study provides an effective reference method for the design of Verilog-based image processing algorithms, which is of great significance in promoting the development of image processing technology.
AbstractList This paper investigates a Verilog-based implementation of a bilinear interpolation algorithm aimed at solving the problem of pixel computation during image enlargement. The bilinear interpolation algorithm, as an effective image processing method, has a wide range of applications in the fields of image processing and computer vision. This algorithm is implemented through the Verilog programming language and includes key steps such as pixel coordinate conversion, nearest neighbor finding, and linear interpolation operations. On hardware platforms such as FPGAs, the use of fixed-point design optimizes the use of resources, improves computational efficiency, and meets real-time requirements. The correctness and effectiveness of the algorithm are verified through simulation tests. This algorithm implementation is characterized by high accuracy and speed and is suitable for real-time image processing applications. This study provides an effective reference method for the design of Verilog-based image processing algorithms, which is of great significance in promoting the development of image processing technology.
Author Lu, Yao
Jin, Yongbo
Yang, Xiaoling
Author_xml – sequence: 1
  givenname: Yao
  surname: Lu
  fullname: Lu, Yao
  email: 102212307@hbut.edu.cn
  organization: Hubei University of Technology,School of Science,Wuhan,China,430068
– sequence: 2
  givenname: Xiaoling
  surname: Yang
  fullname: Yang, Xiaoling
  email: yangxiaoling@hbut.edu.cn
  organization: Hubei University of Technology,School of Science,Wuhan,China,430068
– sequence: 3
  givenname: Yongbo
  surname: Jin
  fullname: Jin, Yongbo
  email: 102312389@hbut.edu.cn
  organization: Hubei University of Technology,School of Science,Wuhan,China,430068
BookMark eNo1j81Kw0AURkdRsNa8gYv4AIlz5_fOsg1VAwU3wW2ZpnfqSJopk2x8ewvq6oPD4cB3z27GNBJjT8BrAO6e22bTNp0BI20tuFA1cGMBrLpihbMOpeYSlZL2mi0ESlNZi-KOFdP0xTmX4qJqt2CwjkMcyeeyHWfK5zT4OaaxXA3HlOP8eSrXfqJDeUEflOOQjg_sNvhhouJvl6x72XTNW7V9f22b1baKDuaqF5pEb3zgRirSITjUeyU9oENEEfbCojVKOad65TUodAcwgMGI3nIX5JI9_mYjEe3OOZ58_t79n5Q_AZdHAQ
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/ICEICT61637.2024.10671174
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Xplore
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Xplore
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9798350384437
EISSN 2836-7782
EndPage 1379
ExternalDocumentID 10671174
Genre orig-research
GroupedDBID 6IE
6IL
6IN
ABLEC
ADZIZ
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
CHZPO
IEGSK
OCL
RIE
RIL
ID FETCH-LOGICAL-i91t-c25e2c6af0634e5ff985b43a1898882fb2787644994c4a51489d1618f62c709f3
IEDL.DBID RIE
IngestDate Wed Aug 27 02:00:19 EDT 2025
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i91t-c25e2c6af0634e5ff985b43a1898882fb2787644994c4a51489d1618f62c709f3
PageCount 5
ParticipantIDs ieee_primary_10671174
PublicationCentury 2000
PublicationDate 2024-July-31
PublicationDateYYYYMMDD 2024-07-31
PublicationDate_xml – month: 07
  year: 2024
  text: 2024-July-31
  day: 31
PublicationDecade 2020
PublicationTitle IEEE International Conference on Electronic Information and Communication Technology (Online)
PublicationTitleAbbrev ICEICT
PublicationYear 2024
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0003211759
Score 1.8783249
Snippet This paper investigates a Verilog-based implementation of a bilinear interpolation algorithm aimed at solving the problem of pixel computation during image...
SourceID ieee
SourceType Publisher
StartPage 1375
SubjectTerms bilinear interpolation
Design methodology
Hardware
Image processing
Image quality
image scaling
Interpolation
Real-time systems
Streaming media
Verilog
Title Bilinear Interpolation Algorithm Based on Verilog
URI https://ieeexplore.ieee.org/document/10671174
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NSwMxEB1sEfGkYsVvVvCa1mSTzeZoS4u9lB6K9FaS7EQL2pXa-vud7LYVDx68hUAgySaZ92Zn3gDco1IFasVZ4NIxuonInBec2SI3NmTeOLRVsQk9GuXTqRlvktWrXBhErILPsB2b1b_8ovTr6CrrRLkzThC6AQ2tszpZa-dQSUVUnTQHcLfR0ewMe_1hb5IR4tBEBIVsb8f_qqRSGZLB0T-ncAytn5S8ZLwzNiewh4tT4N15RIl2mdSxg2Ud2JY8vr2URPpf35MuGakioa5nOmn0zLVgMuhPek9sUwOBzQ1fMS8UCp_ZQEhCogrB5MrJ1PLcEHUVwQm6cARpjJFeWgI_uSmiBH7IhNcPJqRn0FyUCzyHxEnrciIrVjsvfRBOZ4roCS-4496n4QJacbmzj1rlYrZd6eUf_VdwGDe19nNeQ3O1XOMN7Puv1fxzeVt9m29gyo60
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PT8IwFH5RNOpJjRh_OxOvBdq123oUAoGIhMNiuJG2a3WJMoPg3-_rBhgPHrw1PTRt1_Z939t73wO4t0JkNhaUOMo1wZtoiTaMEpUlUrnISG1VWWwiHo2SyUSOV8nqZS6MtbYMPrMN3yz_5WeFWXpXWdPLnVGE0NuwIzhnrSpda-NSCZnXnZR7cLdS0mwOOt1BJ40Qc8RIBRlvrEf4VUulNCW9w39O4gjqP0l5wXhjbo5hy85OgLZzjxPVPKiiB4sqtC14eHspkPa_vgdtNFNZgF3PeNbwoatD2uumnT5ZVUEguaQLYpiwzETKIZbgVjgnE6F5qGgikbwypxleOQQ1UnLDFcKfRGZeBN9FzMQt6cJTqM2KmT2DQHOlE6QrKtaGG8d0HAkkKDSjmhoTunOo--VOPyqdi-l6pRd_9N_Cfj99Gk6Hg9HjJRz4Da68nldQW8yX9hp2zdci_5zflN_pGwM6kfs
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=IEEE+International+Conference+on+Electronic+Information+and+Communication+Technology+%28Online%29&rft.atitle=Bilinear+Interpolation+Algorithm+Based+on+Verilog&rft.au=Lu%2C+Yao&rft.au=Yang%2C+Xiaoling&rft.au=Jin%2C+Yongbo&rft.date=2024-07-31&rft.pub=IEEE&rft.eissn=2836-7782&rft.spage=1375&rft.epage=1379&rft_id=info:doi/10.1109%2FICEICT61637.2024.10671174&rft.externalDocID=10671174