Modified Concept to Achieve Maximum Efficiency of CPU Scheduling Algorithm

Arranging is a champion among the basic deeds of the system head, which is responsible to take decision in order to pick the technique in readied line that will be consigned to CPU. There are various sorts of arranging computations for decision making system. Priority Scheduling Algorithm relies upo...

Celý popis

Uložené v:
Podrobná bibliografia
Vydané v:2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA) s. 660 - 663
Hlavní autori: Chauhan, Himani, Inani, Anunaya
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 01.06.2019
Predmet:
Aerospace electronics
Computational modeling
Conferences
CPU
CPU scheduling algorithms
Estimation
Planning
Program processors
Scheduling algorithms
Turnaround Time
Waiting Time
On-line prístup:Získať plný text
Tagy: Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
Abstract Arranging is a champion among the basic deeds of the system head, which is responsible to take decision in order to pick the technique in readied line that will be consigned to CPU. There are various sorts of arranging computations for decision making system. Priority Scheduling Algorithm relies upon need named to every method. In this paper, booking estimation is recycled so that in similar type concepts the shortest job first count is used.
AbstractList Arranging is a champion among the basic deeds of the system head, which is responsible to take decision in order to pick the technique in readied line that will be consigned to CPU. There are various sorts of arranging computations for decision making system. Priority Scheduling Algorithm relies upon need named to every method. In this paper, booking estimation is recycled so that in similar type concepts the shortest job first count is used.
Author Inani, Anunaya
Chauhan, Himani
Author_xml – sequence: 1
  givenname: Himani
  surname: Chauhan
  fullname: Chauhan, Himani
  organization: CSE Department, GIET, Kota, Rajasthan, India
– sequence: 2
  givenname: Anunaya
  surname: Inani
  fullname: Inani, Anunaya
  organization: CSE Department, GIET, Kota, Rajasthan, India
BookMark eNotz0FPwyAYgGFM9KBzf0Av_IFWPqBAjw2pOrNFE-d5YfCxkrRlqZ1x_96DO723J3nvyPWYRyTkAVgJwOqnlW1tU3IGdWkMB8PZFVnW2oDmBhgoXd2St00OKSYM1ObR43Gmc6aN7xL-IN243zScBtrGmHzC0Z9pjtR-fNFP32E49Wk80KY_5CnN3XBPbqLrv3F56YJsn9utfS3W7y8r26yLVLO5iCIIGY32gHtmgmLMBekMcxDQcReiYFVU0lV7pWX0EmStFQ--0l4JH5RYkMd_NiHi7jilwU3n3WVQ_AHOy0n5
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/ICECA.2019.8821820
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Xplore POP ALL
IEEE Xplore All Conference Proceedings
IEEE Xplore
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Xplore
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9781728101675
1728101670
EndPage 663
ExternalDocumentID 8821820
Genre orig-research
GroupedDBID 6IE
6IL
CBEJK
RIE
RIL
ID FETCH-LOGICAL-i90t-f3d34f87c1eb08d600ad4a80a1dea2adf305f64a5b674fc4149762dc57c63cd63
IEDL.DBID RIE
IngestDate Wed Aug 27 02:46:13 EDT 2025
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i90t-f3d34f87c1eb08d600ad4a80a1dea2adf305f64a5b674fc4149762dc57c63cd63
PageCount 4
ParticipantIDs ieee_primary_8821820
PublicationCentury 2000
PublicationDate 2019-June
PublicationDateYYYYMMDD 2019-06-01
PublicationDate_xml – month: 06
  year: 2019
  text: 2019-June
PublicationDecade 2010
PublicationTitle 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA)
PublicationTitleAbbrev ICECA
PublicationYear 2019
Publisher IEEE
Publisher_xml – name: IEEE
Score 1.6895591
Snippet Arranging is a champion among the basic deeds of the system head, which is responsible to take decision in order to pick the technique in readied line that...
SourceID ieee
SourceType Publisher
StartPage 660
SubjectTerms Aerospace electronics
Computational modeling
Conferences
CPU
CPU scheduling algorithms
Estimation
Planning
Program processors
Scheduling algorithms
Turnaround Time
Waiting Time
Title Modified Concept to Achieve Maximum Efficiency of CPU Scheduling Algorithm
URI https://ieeexplore.ieee.org/document/8821820
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NSwMxEA21ePCk0orf5ODR2N1uNtk9lqVFxZaCVXoraTLTLtiu1G3x55tka0Xw4i2EQMgMybwk780QcmMxPkoRAEvbasq4FsBs3OEMJahQgI1wvnzb65McDJLxOB3WyO1OCwMAnnwGd67p__JNodfuqaxl0aDLN75H9qQUlVbrWwcTpK2HrJt1HFnLed8P_FUxxQeM3uH_pjoizR_lHR3uYsoxqcGyQR77hcnRYkWaVSJDWha0o-c5bID21We-WC9o1-eCcEJKWiDNhi_02frDOKL5jHbeZsUqL-eLJhn1uqPsnm1rILA8DUqGkYk4JlKHMA0SY9GJMlwlgQoNqLYyaLcrCq7iqZAcNbf3HXu6GR1LLSJtRHRC6stiCaeERhCmqBHRYhwuQp3KWEltQhVLQLvWM9JwZpi8V1kuJlsLnP_dfUEOnKUr0tQlqZerNVyRfb0p84_VtXfNFxskkdw
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NTwIxEJ0gmuhJDRi_7cGjlV232-4eyQYCCoRENNxIaaewibAGF-LPt10QY-LFW9M0aTqTdl7b92YAbi3GN4J7SOMHOaZMcaQ27jBqBEqfo41wRfm2147o9aLhMO6X4G6rhUHEgnyG965Z_OXrTC3dU1nNokGXb3wHdl3lrI1a61sJ48W1dtJI6o6u5fxfDP1VM6UIGc3D_012BNUf7R3pb6PKMZRwXoHHbqZTY9EiSdYyQ5JnpK6mKa6QdOVnOlvOSKPIBuGklCQzJOm_kGfrEe2o5hNSf5tkizSfzqowaDYGSYtuqiDQNPZyagIdMBMJ5ePYi7TFJ1IzGXnS1ygfpDZ2wxrOZDjmghnF7I3Hnm9ahULxQGkenEB5ns3xFEiAfmyUMcaiHMZ9FYtQCqV9GQo0dq1nUHFmGL2v81yMNhY4_7v7BvZbg25n1Gn3ni7gwFl9TaG6hHK-WOIV7KlVnn4srgs3fQHj0ZUl
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2019+3rd+International+conference+on+Electronics%2C+Communication+and+Aerospace+Technology+%28ICECA%29&rft.atitle=Modified+Concept+to+Achieve+Maximum+Efficiency+of+CPU+Scheduling+Algorithm&rft.au=Chauhan%2C+Himani&rft.au=Inani%2C+Anunaya&rft.date=2019-06-01&rft.pub=IEEE&rft.spage=660&rft.epage=663&rft_id=info:doi/10.1109%2FICECA.2019.8821820&rft.externalDocID=8821820