A novel fixed-point square root algorithm and its digital hardware design

Square root operation is one of the basic important operation in digital signal processing. It will calculate the square root value from the given input. This operation is known hard to implement in digital hardware because of the complexity of its algorithm. There were many researches related to th...

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Veröffentlicht in:2013 International Conference on ICT for Smart Society (ICISS) S. 1 - 4
1. Verfasser: Putra, Rachmad Vidya Wicaksana
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.06.2013
Schlagworte:
Clocks
Complexity theory
Computer architecture
Delays
Field programmable gate arrays
fixed-point
Hardware
Iterative algorithms
iterative calculation
Logic
low complexity
Novel square root algorithm
Registers
resource-efficient
Signal processing algorithms
simple
ISBN:1479901431, 9781479901432
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:Square root operation is one of the basic important operation in digital signal processing. It will calculate the square root value from the given input. This operation is known hard to implement in digital hardware because of the complexity of its algorithm. There were many researches related to this topic to obtain the optimum design between area consumption and speed. Regarding this condition, we propose an alternative square root algorithm which is based on two approaches, digital binary input decomposition and iterative calculation. Its fixed-point digital hardware implementation is very simple, low complexity, and resource-efficient. It doesn't need any correction adjustments and directly produces accurate value of square root result and remainder in (N/2)+1 clock cycles, which N represents the wordlength of input. This design has been synthesized for FPGA target board Altera Cyclone II EP2C35F672C6 and produced good results in resource consumption and speed.
ISBN:1479901431
9781479901432
DOI:10.1109/ICTSS.2013.6588110