Low power optimization of instruction cache based on tag check reduction
In the embedded microprocessor based systems, the instruction cache dissipates a large percentage of the system power, since the instruction fetching occurs on nearly every clock cycle. This paper proposes a low power optimization method of instruction cache based on tag check reduction. By using th...
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| Vydáno v: | 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) s. 1 - 3 |
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| Jazyk: | angličtina |
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IEEE
01.10.2012
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| ISBN: | 9781467324748, 1467324744 |
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| Abstract | In the embedded microprocessor based systems, the instruction cache dissipates a large percentage of the system power, since the instruction fetching occurs on nearly every clock cycle. This paper proposes a low power optimization method of instruction cache based on tag check reduction. By using the compiler to denote the loops whose length is less than the instruction cache size and adding some simple logic circuits to control the tag array access, the unnecessary tag checks could be reduced and the instruction cache energy consumption could be saved. Experimental results of the SuperV DSP show that this approach could save 20.1% of instruction cache power consumption, with only 0.69% of area increasing and 0.05% of performance degradation. |
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| AbstractList | In the embedded microprocessor based systems, the instruction cache dissipates a large percentage of the system power, since the instruction fetching occurs on nearly every clock cycle. This paper proposes a low power optimization method of instruction cache based on tag check reduction. By using the compiler to denote the loops whose length is less than the instruction cache size and adding some simple logic circuits to control the tag array access, the unnecessary tag checks could be reduced and the instruction cache energy consumption could be saved. Experimental results of the SuperV DSP show that this approach could save 20.1% of instruction cache power consumption, with only 0.69% of area increasing and 0.05% of performance degradation. |
| Author | Tiejun Zhang Lidan Bao Chaohuan Hou Quanquan Li |
| Author_xml | – sequence: 1 surname: Quanquan Li fullname: Quanquan Li email: liquanquan2007@126.com organization: Grad. Univ. of Chinese Acad. of Sci., Beijing, China – sequence: 2 surname: Lidan Bao fullname: Lidan Bao organization: Grad. Univ. of Chinese Acad. of Sci., Beijing, China – sequence: 3 surname: Tiejun Zhang fullname: Tiejun Zhang organization: Digital Syst. Integration Lab., Inst. of Acoust., Beijing, China – sequence: 4 surname: Chaohuan Hou fullname: Chaohuan Hou organization: Digital Syst. Integration Lab., Inst. of Acoust., Beijing, China |
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| Snippet | In the embedded microprocessor based systems, the instruction cache dissipates a large percentage of the system power, since the instruction fetching occurs on... |
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| SubjectTerms | Arrays compiler support Degradation Digital signal processing low power instruction cache Microprocessors Optimization Power demand Program processors tag check reduction |
| Title | Low power optimization of instruction cache based on tag check reduction |
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