Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy

In this paper, we propose a quality metric for an NoC and model the yield and cost of a spare-enhanced multi-core chip subject to a given quality constraint. Our experiments show that the overall quality of a mesh-based NoC depends more on the reliability of the inner links than the outer links; the...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:2010 28th VLSI Test Symposium (VTS) S. 194 - 199
Hauptverfasser: Shamshiri, Saeed, Kwang-Ting Cheng
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.04.2010
Schlagworte:
Costs
Field programmable gate arrays
Logic devices
Manufacturing processes
Multicore processing
Network-on-a-chip
NoC
non-uniform spare distributtion
Programmable logic arrays
quality analysis
Redundancy
SoC
Telecommunication network reliability
Wires
yield and cost modeling
ISBN:9781424466498, 1424466490
ISSN:1093-0167
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:In this paper, we propose a quality metric for an NoC and model the yield and cost of a spare-enhanced multi-core chip subject to a given quality constraint. Our experiments show that the overall quality of a mesh-based NoC depends more on the reliability of the inner links than the outer links; therefore, a non-uniform distribution of spare wires could be more effective and cost efficient than a uniform approach.
ISBN:9781424466498
1424466490
ISSN:1093-0167
DOI:10.1109/VTS.2010.5469579