An Embedded Programmable Processor for Compressive Sensing Applications
An application specific programmable processor is designed based on the analysis of a set of greedy recovery Compressive Sensing (CS) algorithms. The solution is flexible and customizable for a wide range of problem dimensions, as well as algorithms. The versatility of the approach is demonstrated b...
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| Vydáno v: | 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) s. 1 - 5 |
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01.10.2018
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| Abstract | An application specific programmable processor is designed based on the analysis of a set of greedy recovery Compressive Sensing (CS) algorithms. The solution is flexible and customizable for a wide range of problem dimensions, as well as algorithms. The versatility of the approach is demonstrated by implementing Orthogonal Matching Pursuits, Approximate Messaging Passing and Normalized Iterative Hard Thresholding algorithms, all using a high-level language. Transported Triggered Architecture (TTA) framework is employed for the efficient implementation of macro operations shared by the algorithms. The performance of the CS algorithms on ARM Cortex-A15 and NIOS II processors has also been investigated, and empirical comparisons are presented. The flexible hardware design implemented on an FPGA achieves up to 7.80Ksample/s recovery at a power dissipation of 42\muJ/sample and beats both ARM and NIOS in total power consumption. |
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| AbstractList | An application specific programmable processor is designed based on the analysis of a set of greedy recovery Compressive Sensing (CS) algorithms. The solution is flexible and customizable for a wide range of problem dimensions, as well as algorithms. The versatility of the approach is demonstrated by implementing Orthogonal Matching Pursuits, Approximate Messaging Passing and Normalized Iterative Hard Thresholding algorithms, all using a high-level language. Transported Triggered Architecture (TTA) framework is employed for the efficient implementation of macro operations shared by the algorithms. The performance of the CS algorithms on ARM Cortex-A15 and NIOS II processors has also been investigated, and empirical comparisons are presented. The flexible hardware design implemented on an FPGA achieves up to 7.80Ksample/s recovery at a power dissipation of 42\muJ/sample and beats both ARM and NIOS in total power consumption. |
| Author | Silven, Olli Hautala, Ilkka Safarpour, Mehdi |
| Author_xml | – sequence: 1 givenname: Mehdi surname: Safarpour fullname: Safarpour, Mehdi organization: Center for Machine Vision and Signal Analysis, University of Oulu, Oulu, Finland – sequence: 2 givenname: Ilkka surname: Hautala fullname: Hautala, Ilkka organization: Center for Machine Vision and Signal Analysis, University of Oulu, Oulu, Finland – sequence: 3 givenname: Olli surname: Silven fullname: Silven, Olli organization: Center for Machine Vision and Signal Analysis, University of Oulu, Oulu, Finland |
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| PublicationTitle | 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) |
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| Snippet | An application specific programmable processor is designed based on the analysis of a set of greedy recovery Compressive Sensing (CS) algorithms. The solution... |
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| SubjectTerms | Approximation algorithms Compressed sensing Compressive Sensing Embedded Processor IoT Matching pursuit algorithms Power demand Registers Signal Reconstruction Software algorithms Sparse matrices |
| Title | An Embedded Programmable Processor for Compressive Sensing Applications |
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