A Memory-Efficient CAVLC Decoding Scheme for H.264/AVC

This paper presents a memory-efficient CAVLC decoding architecture for H.264/AVC. In the proposed architecture, not only the memory space is reduced for decoding the syntax elements such as coeff token, total zero, and run before, but also the decode efficiency is improved. After the analysis of the...

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Veröffentlicht in:2008 10th International Conference on Advanced Communication Technology Jg. 2; S. 1135 - 1138
Hauptverfasser: Yanling Chen, Xixin Cao, Xiaoming Peng, Chungan Peng, Dunshan Yu, Xing Zhang
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.02.2008
Schlagworte:
Arithmetic
Automatic voltage control
Clocks
coeff_token
Computer architecture
Computer industry
Context-based adaptive variable length coding
Decoding
Frequency
Memory architecture
Microelectronics
run_before
SignTrail
Table lookup
total_zero
ISBN:8955191367, 9788955191363, 8955191359, 9788955191356
ISSN:1738-9445
Online-Zugang:Volltext
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Abstract This paper presents a memory-efficient CAVLC decoding architecture for H.264/AVC. In the proposed architecture, not only the memory space is reduced for decoding the syntax elements such as coeff token, total zero, and run before, but also the decode efficiency is improved. After the analysis of the decoding principle of the CAVLC, we simplify the coeff-token VLD table and propose a new coeff-token VLD based on arithmetic operation and the look-up table combination architecture. The run-before VLD can used the same principle as the proposed coeff-token VLD. Otherwise, the proposed scheme also adope the zero block skipping technique and multiple symbols decoding scheme when decoding SignTrail. The simulation results show that our system can run at I68MHz clock frequency and the average cycles for decoding one macro-block is 136 cycles. The proposed architecture can achieves an approximate 39-53% savings in memory access without video quality degrading.
AbstractList This paper presents a memory-efficient CAVLC decoding architecture for H.264/AVC. In the proposed architecture, not only the memory space is reduced for decoding the syntax elements such as coeff token, total zero, and run before, but also the decode efficiency is improved. After the analysis of the decoding principle of the CAVLC, we simplify the coeff-token VLD table and propose a new coeff-token VLD based on arithmetic operation and the look-up table combination architecture. The run-before VLD can used the same principle as the proposed coeff-token VLD. Otherwise, the proposed scheme also adope the zero block skipping technique and multiple symbols decoding scheme when decoding SignTrail. The simulation results show that our system can run at I68MHz clock frequency and the average cycles for decoding one macro-block is 136 cycles. The proposed architecture can achieves an approximate 39-53% savings in memory access without video quality degrading.
Author Xixin Cao
Chungan Peng
Yanling Chen
Xiaoming Peng
Dunshan Yu
Xing Zhang
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  organization: Sch. of Software & Microelectron., Peking Univ., Beijing
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  surname: Xing Zhang
  fullname: Xing Zhang
  organization: Sch. of Software & Microelectron., Peking Univ., Beijing
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Snippet This paper presents a memory-efficient CAVLC decoding architecture for H.264/AVC. In the proposed architecture, not only the memory space is reduced for...
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StartPage 1135
SubjectTerms Arithmetic
Automatic voltage control
Clocks
coeff_token
Computer architecture
Computer industry
Context-based adaptive variable length coding
Decoding
Frequency
Memory architecture
Microelectronics
run_before
SignTrail
Table lookup
total_zero
Title A Memory-Efficient CAVLC Decoding Scheme for H.264/AVC
URI https://ieeexplore.ieee.org/document/4493966
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