An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning

The considerable computational complexity of sequential Monte Carlo (SMC) methods is a major obstacle when implementing them on CPU-based resource constrained embedded systems. Hybrid CPU/FPGA systems, on the other hand, are a more suitable target, as they can efficiently execute both the control-ce...

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Veröffentlicht in:2009 International Conference on Field-Programmable Technology S. 175 - 182
Hauptverfasser: Happe, Markus, Lubbers, Enno, Platzner, Marco
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.12.2009
Schlagworte:
Computational complexity
Field programmable gate arrays
Hardware
Monte Carlo methods
Operating systems
Particle filters
Particle tracking
Runtime
Sliding mode control
State estimation
ISBN:9781424443758, 142444375X
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Abstract The considerable computational complexity of sequential Monte Carlo (SMC) methods is a major obstacle when implementing them on CPU-based resource constrained embedded systems. Hybrid CPU/FPGA systems, on the other hand, are a more suitable target, as they can efficiently execute both the control-centric sequential as well as the data-parallel parts of an SMC application. Determining the optimal HW/SW partitioning is challenging in general, and since in most cases the optimal partitioning is data-dependent even impossible with a design time approach. In this paper, we present a framework for implementing SMC methods on CPU/FPGA based systems such as modern platform FPGAs. Based on a multithreaded programming model, our framework allows for an easy design space exploration with respect to the HW/SW partitioning. Additionally, an SMC application can adaptively switch between several partitionings during run-time to react to changing input data and performance requirements. To show its feasibility and evaluate its performance and area requirements, we demonstrate the framework on two real-world case studies and show that partial reconfiguration can be effectively and transparently used for realizing adaptive HW/SW systems.
AbstractList The considerable computational complexity of sequential Monte Carlo (SMC) methods is a major obstacle when implementing them on CPU-based resource constrained embedded systems. Hybrid CPU/FPGA systems, on the other hand, are a more suitable target, as they can efficiently execute both the control-centric sequential as well as the data-parallel parts of an SMC application. Determining the optimal HW/SW partitioning is challenging in general, and since in most cases the optimal partitioning is data-dependent even impossible with a design time approach. In this paper, we present a framework for implementing SMC methods on CPU/FPGA based systems such as modern platform FPGAs. Based on a multithreaded programming model, our framework allows for an easy design space exploration with respect to the HW/SW partitioning. Additionally, an SMC application can adaptively switch between several partitionings during run-time to react to changing input data and performance requirements. To show its feasibility and evaluate its performance and area requirements, we demonstrate the framework on two real-world case studies and show that partial reconfiguration can be effectively and transparently used for realizing adaptive HW/SW systems.
Author Lubbers, Enno
Platzner, Marco
Happe, Markus
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  givenname: Markus
  surname: Happe
  fullname: Happe, Markus
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  givenname: Enno
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  givenname: Marco
  surname: Platzner
  fullname: Platzner, Marco
  email: platznerg@uni-paderborn.de
  organization: International Graduate School, University of Paderborn, Germany
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Snippet The considerable computational complexity of sequential Monte Carlo (SMC) methods is a major obstacle when implementing them on CPU-based resource constrained...
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StartPage 175
SubjectTerms Computational complexity
Field programmable gate arrays
Hardware
Monte Carlo methods
Operating systems
Particle filters
Particle tracking
Runtime
Sliding mode control
State estimation
Title An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning
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