Low Complexity Bit-Parallel Multiplier for a Class of Finite Fields

This short paper summarizes our recent results on construction of low-complexity bit-parallel finite field multiplier using polynomial basis. The complexity and time delay of the proposed multipliers are lower than those of the similar proposals.

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Published in:2006 International Conference on Communications, Circuits, and Systems proceedings : Guilin University of Electronic Technology (GUET), Guilin Bravo Hotel, Guilin, China, June 25-28, 2006 Vol. 4; pp. 2565 - 2568
Main Author: Huapeng Wu
Format: Conference Proceeding
Language:English
Published: IEEE 01.06.2006
Subjects:
ISBN:9780780395848, 0780395840
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Abstract This short paper summarizes our recent results on construction of low-complexity bit-parallel finite field multiplier using polynomial basis. The complexity and time delay of the proposed multipliers are lower than those of the similar proposals.
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Author Huapeng Wu
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PublicationTitle 2006 International Conference on Communications, Circuits, and Systems proceedings : Guilin University of Electronic Technology (GUET), Guilin Bravo Hotel, Guilin, China, June 25-28, 2006
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Snippet This short paper summarizes our recent results on construction of low-complexity bit-parallel finite field multiplier using polynomial basis. The complexity...
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StartPage 2565
SubjectTerms Arithmetic
Concurrent computing
Delay effects
Design optimization
Elliptic curve cryptography
Galois fields
Logic
Polynomials
Proposals
Very large scale integration
Title Low Complexity Bit-Parallel Multiplier for a Class of Finite Fields
URI https://ieeexplore.ieee.org/document/4064444
Volume 4
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