Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary coding

In this paper, an efficient implementation of the concurrent decision feedback equalizer (DFE) is carried out using offset binary coding (OBC) based on distributed arithmetic (DA). The concurrent decision feedback equalizer is employed in multi-gigabit systems which uses the principle of paralleliza...

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Vydáno v:2016 20th International Symposium on VLSI Design and Test (VDAT) s. 1 - 6
Hlavní autoři: Khan, M. Tasleem, Ahamed, Shaik Rafi, Chatterjee, Amitabh
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.05.2016
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Abstract In this paper, an efficient implementation of the concurrent decision feedback equalizer (DFE) is carried out using offset binary coding (OBC) based on distributed arithmetic (DA). The concurrent decision feedback equalizer is employed in multi-gigabit systems which uses the principle of parallelization. However, the hardware complexity of adders and multipliers rises quadratically with parallelization factor. In our proposed technique, we have used look-up table (LUT) and shift-accumulate block as per DA requirement. In order to reduce the access time of LUT, we employed OBC scheme which therefore improves the speed of filtering operation. Moreover, it also reduces the chip area for LUT based filter design. Furthermore, our design provides significant reduction of hardware complexities in spite of slight increase in address decoding logic of OBC combinations while LUT complexity grows linearly. By doing so, the concurrent nature of look-ahead DFE is unaltered and can still be used for multi-gigabit applications. We have estimated hardware complexity and critical path of our design and compared with best existing schemes. Synthesis is performed in UMC 180 nm CMOS technology using cadence RTL compiler for the feedback filter length N = 4, 6 and 8. The proposed structure of concurrent look-ahead DFE is found to have low area in comparison to other schemes for any length of the feedback filter.
AbstractList In this paper, an efficient implementation of the concurrent decision feedback equalizer (DFE) is carried out using offset binary coding (OBC) based on distributed arithmetic (DA). The concurrent decision feedback equalizer is employed in multi-gigabit systems which uses the principle of parallelization. However, the hardware complexity of adders and multipliers rises quadratically with parallelization factor. In our proposed technique, we have used look-up table (LUT) and shift-accumulate block as per DA requirement. In order to reduce the access time of LUT, we employed OBC scheme which therefore improves the speed of filtering operation. Moreover, it also reduces the chip area for LUT based filter design. Furthermore, our design provides significant reduction of hardware complexities in spite of slight increase in address decoding logic of OBC combinations while LUT complexity grows linearly. By doing so, the concurrent nature of look-ahead DFE is unaltered and can still be used for multi-gigabit applications. We have estimated hardware complexity and critical path of our design and compared with best existing schemes. Synthesis is performed in UMC 180 nm CMOS technology using cadence RTL compiler for the feedback filter length N = 4, 6 and 8. The proposed structure of concurrent look-ahead DFE is found to have low area in comparison to other schemes for any length of the feedback filter.
Author Chatterjee, Amitabh
Khan, M. Tasleem
Ahamed, Shaik Rafi
Author_xml – sequence: 1
  givenname: M. Tasleem
  surname: Khan
  fullname: Khan, M. Tasleem
  email: tasleem@iitg.ernet.in
  organization: Dept. of Electron. & Electr. Eng., India Inst. of Technol. Guwahati, Guwahati, India
– sequence: 2
  givenname: Shaik Rafi
  surname: Ahamed
  fullname: Ahamed, Shaik Rafi
  email: rafiahamed@iitg.ernet.in
  organization: Dept. of Electron. & Electr. Eng., India Inst. of Technol. Guwahati, Guwahati, India
– sequence: 3
  givenname: Amitabh
  surname: Chatterjee
  fullname: Chatterjee, Amitabh
  email: amitabh_c@iitg.ernet.in
  organization: Dept. of Electron. & Electr. Eng., India Inst. of Technol. Guwahati, Guwahati, India
BookMark eNotj8lOAzEQRI0EBwj5glz8AzO0PZ7FxygEiBSJQyKukZd2sDJjh1kO8PU4Sk7V6up-qnoi9yEGJGTBIGcM5Mtm9_W63OccWJU3UImm4ndkLuuGlSCBCc7FIzmunfPGYxip784tdmlSo4-BRkdNDGbq-4vZxnhS36gstWj8cDlwiFYrc6L4M6nW_2FPp8GHY_p0A45U-6D63wSxaflMHpxqB5zfdEZ2b-v96iPbfr5vVstt5iWMmTaVM6B5wWtuQTgtUSmjCp2yKoGqZiikKaFmFhhrAGvgUgpXsoazwhQzsrhSPSIezr3vUoLDrXzxD8-1Vhg
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/ISVDAT.2016.8064862
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Xplore POP ALL
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 9781509014224
1509014225
EndPage 6
ExternalDocumentID 8064862
Genre orig-research
GroupedDBID 6IE
6IL
CBEJK
RIE
RIL
ID FETCH-LOGICAL-i90t-bc6fc0b23272d04fb9eaaca3b224a4ea71e49c5071d01180e702994f518213c3
IEDL.DBID RIE
IngestDate Wed Jun 26 19:24:14 EDT 2024
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i90t-bc6fc0b23272d04fb9eaaca3b224a4ea71e49c5071d01180e702994f518213c3
PageCount 6
ParticipantIDs ieee_primary_8064862
PublicationCentury 2000
PublicationDate 2016-May
PublicationDateYYYYMMDD 2016-05-01
PublicationDate_xml – month: 05
  year: 2016
  text: 2016-May
PublicationDecade 2010
PublicationTitle 2016 20th International Symposium on VLSI Design and Test (VDAT)
PublicationTitleAbbrev ISVDAT
PublicationYear 2016
Publisher IEEE
Publisher_xml – name: IEEE
Score 1.6422118
Snippet In this paper, an efficient implementation of the concurrent decision feedback equalizer (DFE) is carried out using offset binary coding (OBC) based on...
SourceID ieee
SourceType Publisher
StartPage 1
SubjectTerms Adders
Complexity theory
decision feedback equalizer (DFE)
Decision feedback equalizers
Distributed arithmetic (DA)
Field-flow fractionation
Hardware
Indexes
look-up table (LUT)
offset binary coding (OBC)
Table lookup
Title Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary coding
URI https://ieeexplore.ieee.org/document/8064862
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PS8MwFA5zePCksom_ycGj3dqmNu1RdENBxmBDdhsvycso6iZd58G_3pe0TgQv3kJoEngh73tJv_c9xq5SaSz5QBEooOOWKGoRCNsAMxBSSZUl4CXzn-RolM1m-bjFrre5MIjoyWfYc03_L9-s9MY9lfUzws_MOdwdKdM6V6sREorCvP84eb6_nTq2VtprvvxVMsUjxnD_f2sdsO5P6h0fb0HlkLVw2WGLgRd6oAG8ePsmfDuL8pXldKHVtcgSf6WIGci7Gm6a0jnc0kQK9AtHnz75iSV3VPcFjbRrrLjy-bg0iVuuyybDwfTuIWgqJARFHlaB0qnVoaKgSMYmTKzKEUCDUITLkCDICJNcu4jPeKk3lCGhT2Jv6FIRCS2OWHu5WuIx40roOJcgjGOtSQMqBsJ1tBaQHEIsT1jHmWj-XktgzBvrnP7dfcb23C7UvMBz1q7KDV6wXf1RFevy0u_bFyjCnjA
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NTwIxEG0ImuhJDRi_7cGjC8tuobtHoxCISEgghhuZtlNCVDCwePDXO-2uGBMv3ppm2ybTdN60--YNYzctaSz5wDhQQMdNKGoRCNsAE4ilkioR4CXz-3IwSCaTdFhit9tcGET05DOsuab_l2-WeuOeyuoJ4WfiHO5OU4gozLO1CimhRpjWe6Pnh7ux42u1asW3v4qmeMzoHPxvtUNW_Um-48MtrByxEi4qbNb2Ug80gM_fvinfzqZ8aTldaXUus8RfKWYG8q-Gm6J4Drc0kQL9wtEnUH7iijuy-4xG2jVmXPmMXJrELVdlo057fN8NihoJwTwNs0DpltWhorBIRiYUVqUIoCFWhMwgEGQDRapdzGe82BvKkPBH2CZdKxqxjo9ZebFc4AnjKtZRKiE2jrcmDagICNnRWkByCZE8ZRVnoul7LoIxLaxz9nf3Ndvrjp_6035v8HjO9t2O5CzBC1bOVhu8ZLv6I5uvV1d-D78AjUChdw
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2016+20th+International+Symposium+on+VLSI+Design+and+Test+%28VDAT%29&rft.atitle=Efficient+implementation+of+concurrent+lookahead+decision+feedback+equalizer+using+offset+binary+coding&rft.au=Khan%2C+M.+Tasleem&rft.au=Ahamed%2C+Shaik+Rafi&rft.au=Chatterjee%2C+Amitabh&rft.date=2016-05-01&rft.pub=IEEE&rft.spage=1&rft.epage=6&rft_id=info:doi/10.1109%2FISVDAT.2016.8064862&rft.externalDocID=8064862