An Efficient FPGA Implementation of a Real-Time Image Generator Using Simultaneous Video Memory Read/Write Access and Fast Physical Addressing

This paper presents an FPGA implementation of an advanced real-time architecture for generating video signals from microprocessor-based systems. This architecture is a hardware/software solution for high-speed image processing systems, which require a significant recording time and uses a reduced ar...

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Vydáno v:Fifth International Conference on MEMS, NANO, and Smart Systems : Dubai, UAE, 28-30 December 2009 s. 265 - 269
Hlavní autoři: Maamoun, Mountassar, Meraghni, Abdelhamid, Beguenane, Rachid
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.12.2009
Témata:
Decision support systems
Field programmable gate arrays
Image generation
Micromechanical devices
Read-write memory
ISBN:9781424456154, 1424456150, 0769539386, 9780769539386
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Shrnutí:This paper presents an FPGA implementation of an advanced real-time architecture for generating video signals from microprocessor-based systems. This architecture is a hardware/software solution for high-speed image processing systems, which require a significant recording time and uses a reduced area of physical addressing of microprocessor-based systems. This solution investigates both the Fast Physical Addressing and the simultaneous video memory read-write system. This latter is ensured by a split of the hardware video memory in separate capacities and by association of a selecting circuit.
ISBN:9781424456154
1424456150
0769539386
9780769539386
DOI:10.1109/ICMENS.2009.65