ISIS: a genetic algorithm based technique for custom on-chip interconnection network synthesis

On-chip packet switched interconnection networks (or network-on-chip (NoC)) have been proposed as a solution to the communication challenges of system-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for...

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Bibliographic Details

Published in:	18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design pp. 623 - 628
Main Authors:	Srinivasan, K., Chatha, K.S.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 2005
Subjects:	Communication switching Cost function Energy consumption Genetic algorithms Intersymbol interference Multiprocessor interconnection networks Network synthesis Network-on-a-chip Packet switching System-on-a-chip
ISBN:	0769522645, 9780769522647
ISSN:	1063-9667
Online Access:	Get full text
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