ISIS: a genetic algorithm based technique for custom on-chip interconnection network synthesis

On-chip packet switched interconnection networks (or network-on-chip (NoC)) have been proposed as a solution to the communication challenges of system-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for...

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Published in:18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design pp. 623 - 628
Main Authors: Srinivasan, K., Chatha, K.S.
Format: Conference Proceeding
Language:English
Published: IEEE 2005
Subjects:
Communication switching
Cost function
Energy consumption
Genetic algorithms
Intersymbol interference
Multiprocessor interconnection networks
Network synthesis
Network-on-a-chip
Packet switching
System-on-a-chip
ISBN:0769522645, 9780769522647
ISSN:1063-9667
Online Access:Get full text
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Abstract On-chip packet switched interconnection networks (or network-on-chip (NoC)) have been proposed as a solution to the communication challenges of system-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents ISIS, a novel genetic algorithm (GA) based technique for custom NoC synthesis that optimizes both the power consumption and area of the design subject 10 the performance constraints, and generates a custom NoC topology and mapping of the communication traces on the architecture. ISIS solves a multi-objective optimization problem by minimizing a cost function expressed as a linear combination of the cost incurred due to power consumption and area. We present a detailed analysis of the quality of the results and the solution times of the proposed technique by extensive experimentation with realistic benchmarks and comparisons with optimal MILP solutions.
AbstractList On-chip packet switched interconnection networks (or network-on-chip (NoC)) have been proposed as a solution to the communication challenges of system-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents ISIS, a novel genetic algorithm (GA) based technique for custom NoC synthesis that optimizes both the power consumption and area of the design subject 10 the performance constraints, and generates a custom NoC topology and mapping of the communication traces on the architecture. ISIS solves a multi-objective optimization problem by minimizing a cost function expressed as a linear combination of the cost incurred due to power consumption and area. We present a detailed analysis of the quality of the results and the solution times of the proposed technique by extensive experimentation with realistic benchmarks and comparisons with optimal MILP solutions.
Author Chatha, K.S.
Srinivasan, K.
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  surname: Chatha
  fullname: Chatha, K.S.
  organization: Dept. of Comput. Sci. & Eng., Arizona State Univ., Tempe, AZ, USA
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Snippet On-chip packet switched interconnection networks (or network-on-chip (NoC)) have been proposed as a solution to the communication challenges of system-on-chip...
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StartPage 623
SubjectTerms Communication switching
Cost function
Energy consumption
Genetic algorithms
Intersymbol interference
Multiprocessor interconnection networks
Network synthesis
Network-on-a-chip
Packet switching
System-on-a-chip
Title ISIS: a genetic algorithm based technique for custom on-chip interconnection network synthesis
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