An Efficient ASIC Implementation of CLEFIA Encryption/Decryption Algorithm With Novel S-Box Architectures - Saravanan, P.; Rani, S. Subha; Rekha, S. Shanthi; Jatana, H.S. (2019 IEEE 1st International Conference on Energy, Systems and Information Processing (ICESIP), 2019)
The demand for lightweight cryptography is inevitable considering the need for security and privacy in the resource constrained environment like active smart devices, RFID and smart edge nodes in Internet of Things (IoT). CLEFIA is one of the ISO/IEC 29191-2 standard lightweight cipher suitable for these applications. For the first time in literature, a novel Composite Field Approach (CFA) based architecture with 4-stage pipelining is derived for CLEFIA Substitution-1 box (S1 box) and a unique Algebraic Normal Form (ANF) based implementation is done for CLEFIA Substitution-0 box (S0 box). The proposed S-box architectures have achieved lowest area in-terms of Gate Equivalence (GE) compared to the traditional implementations. Thereby, a low-cost top-level CLEFIA encryption/decryption architecture is implemented by integrating the novel sub-blocks and its performance is analyzed. The proposed architecture has achieved a low area of 3282 GE, a high throughput of 592.58 Mbps and a low power consumption of 6.1 mW when synthesized using Semi-Conductor Laboratory (SCL) 180nm technology library. As a proof of concept, a working model of the proposed encryption/decryption architecture is prototyped on Basys-3 FPGA with the help of LogiCore VIO.