Design and Implementation of a 1.5Gsps Digital Channelized Receiver

Based on the derivation of the efficient implementation structure of the frequency domain polyphase filter digital channelized receiver, a digital channelized receiver was achieved on the hardware platform with I/Q sampling, 1500Msps, 64channels. In order to ensure good performance of the system, op...

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Vydané v:	2010 2nd International Conference on Information Engineering and Computer Science s. 1 - 4
Hlavní autori:	Xu, Shichao, Liu, Guoman, Gao, Meiguo, Qin, Guo Jie
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 01.12.2010
Predmet:	Clocks Data processing Field programmable gate arrays Frequency domain analysis Hardware Low pass filters Receivers
ISBN:	1424479398, 9781424479399
ISSN:	2156-7379
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