Design and Implementation of a 1.5Gsps Digital Channelized Receiver

Based on the derivation of the efficient implementation structure of the frequency domain polyphase filter digital channelized receiver, a digital channelized receiver was achieved on the hardware platform with I/Q sampling, 1500Msps, 64channels. In order to ensure good performance of the system, op...

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Veröffentlicht in:2010 2nd International Conference on Information Engineering and Computer Science S. 1 - 4
Hauptverfasser: Xu, Shichao, Liu, Guoman, Gao, Meiguo, Qin, Guo Jie
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.12.2010
Schlagworte:
Clocks
Data processing
Field programmable gate arrays
Frequency domain analysis
Hardware
Low pass filters
Receivers
ISBN:1424479398, 9781424479399
ISSN:2156-7379
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Zusammenfassung:Based on the derivation of the efficient implementation structure of the frequency domain polyphase filter digital channelized receiver, a digital channelized receiver was achieved on the hardware platform with I/Q sampling, 1500Msps, 64channels. In order to ensure good performance of the system, optimization of the processor speed and processor resources was fully considered during the design process of the whole system. The actual ultra-wideband signal test results show that the digital channelized receiver is in good performance.
ISBN:1424479398
9781424479399
ISSN:2156-7379
DOI:10.1109/ICIECS.2010.5677721