Efficient check node update implementation for normalized min-sum algorithm

This paper has presented various min-sum related LDPC decoding algorithms and their typical hardware architectures of check node update in the scenario of parallel implementation. The m-to-2m decoder has been introduced to generate more efficient new hardware implementations of check node update, wh...

Full description

Bibliographic Details

Published in:	TENCON 2007 - 2007 IEEE Region 10 Conference pp. 1 - 4
Main Authors:	Lu Xin, Liang Yongsheng, Xu Jun
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.10.2007
Subjects:	Additive white noise AWGN Baseband Code standards Gaussian channels Hardware Information technology Iterative decoding Parity check codes Turbo codes
ISBN:	1424412714, 9781424412716
ISSN:	2159-3442
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!