High-Speed Adaptive Turbo Decoding Algorithm and Its Implementation

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/Q...

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Veröffentlicht in:2006 Asia-Pacific Conference on Communications S. 1 - 5
Hauptverfasser: Duk Gun Choi, Jin Hee Jeong, Min Hyuk Kim, Ji Won Jung
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.08.2006
Schlagworte:
Channel coding
Delay
Energy consumption
Field programmable gate arrays
Hardware
Iterative algorithms
Iterative decoding
Modulation coding
Quadrature phase shift keying
Turbo codes
ISBN:1424405734, 9781424405732
ISSN:2163-0771
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Zusammenfassung:In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improved the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times
ISBN:1424405734
9781424405732
ISSN:2163-0771
DOI:10.1109/APCC.2006.255799