Scaling analysis of solving algorithms for canonical problem of dispatching in the context of dynamic programming
The paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. The models are applied for solving a canonical problem of dispatching where the computation time significantly depends on the problem scale factor. T...
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| Vydané v: | 2017 Internet Technologies and Applications (ITA) s. 181 - 184 |
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| Hlavní autori: | , , , , |
| Médium: | Konferenčný príspevok.. |
| Jazyk: | English |
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01.09.2017
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| Abstract | The paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. The models are applied for solving a canonical problem of dispatching where the computation time significantly depends on the problem scale factor. The parallel algorithms of NP-hard problem of dispatching are complicate and require intensive RAM data exchange. In order to reduce the computation time, it is suggested to use FPGA as a coprocessor providing massively parallel computation and increase the operational performance of the system in one order. |
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| AbstractList | The paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. The models are applied for solving a canonical problem of dispatching where the computation time significantly depends on the problem scale factor. The parallel algorithms of NP-hard problem of dispatching are complicate and require intensive RAM data exchange. In order to reduce the computation time, it is suggested to use FPGA as a coprocessor providing massively parallel computation and increase the operational performance of the system in one order. |
| Author | Chakirov, Roustiam Fedosenko, Yuriy S. Reznikov, Mikhail B. Plekhov, Aleksandr S. Houlden, Nigel |
| Author_xml | – sequence: 1 givenname: Yuriy S. surname: Fedosenko fullname: Fedosenko, Yuriy S. organization: Volga State Univ. of Water Transp., Nizhny Novgorod, Russia – sequence: 2 givenname: Mikhail B. surname: Reznikov fullname: Reznikov, Mikhail B. organization: Volga State Univ. of Water Transp., Nizhny Novgorod, Russia – sequence: 3 givenname: Aleksandr S. surname: Plekhov fullname: Plekhov, Aleksandr S. organization: Alekseev Nizhny Novgorod State Tech. Univ., Nizhny Novgorod, Russia – sequence: 4 givenname: Roustiam surname: Chakirov fullname: Chakirov, Roustiam organization: Bonn-Rhein-Sieg Univ. of Appl. Sci., St. Augustin, Germany – sequence: 5 givenname: Nigel surname: Houlden fullname: Houlden, Nigel organization: Glyndwr Univ., Wrexham, UK |
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| Snippet | The paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. The... |
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| StartPage | 181 |
| SubjectTerms | calculations modeling Computational modeling discrete optimisation Dispatching dispatching problem Dynamic programming Field programmable gate arrays Graphics processing units massively parallel calculations Random access memory |
| Title | Scaling analysis of solving algorithms for canonical problem of dispatching in the context of dynamic programming |
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