Design of high performance 8 bit binary multiplier using vedic multiplication algorithm with 16 nm technology
Vedic mathematics is a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras or formulae. This technique is very useful for performing tedious mathematical operations at a very fast rate. Motivated by this ancient mathematical system, a high speed lo...
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| Vydáno v: | 2017 1st International Conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech) s. 1 - 5 |
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IEEE
01.04.2017
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| Abstract | Vedic mathematics is a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras or formulae. This technique is very useful for performing tedious mathematical operations at a very fast rate. Motivated by this ancient mathematical system, a high speed low power 8-bit digital multiplier has been proposed in this paper based on Vedic multiplication algorithms with a very efficient low power 16 nm technology. To establish the superiority of the proposed design over the existing techniques, the performance of the designed multiplier has been compared with the performances of the multipliers designed with Multiple Channel CMOS (McCMOS) technology and 65 nm technology. All the simulations have been carried out using T-Spice simulation environment. Simulation results shows that the Power Delay Product of the proposed 8 bit Vedic multiplier using 16nm technology is much lesser as compared to the other technologies as mentioned above and thus outperforms them. The proposed technique will be very useful for designing low power high speed ALU unit in future. |
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| AbstractList | Vedic mathematics is a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras or formulae. This technique is very useful for performing tedious mathematical operations at a very fast rate. Motivated by this ancient mathematical system, a high speed low power 8-bit digital multiplier has been proposed in this paper based on Vedic multiplication algorithms with a very efficient low power 16 nm technology. To establish the superiority of the proposed design over the existing techniques, the performance of the designed multiplier has been compared with the performances of the multipliers designed with Multiple Channel CMOS (McCMOS) technology and 65 nm technology. All the simulations have been carried out using T-Spice simulation environment. Simulation results shows that the Power Delay Product of the proposed 8 bit Vedic multiplier using 16nm technology is much lesser as compared to the other technologies as mentioned above and thus outperforms them. The proposed technique will be very useful for designing low power high speed ALU unit in future. |
| Author | Dey, Koyel Chattopadhyay, Sudipta |
| Author_xml | – sequence: 1 givenname: Koyel surname: Dey fullname: Dey, Koyel email: koyeldeykoyeldey1992@gmail.com organization: Dept. of Electron. & Telecommun. Eng., Jadavpur Univ., Kolkata, India – sequence: 2 givenname: Sudipta surname: Chattopadhyay fullname: Chattopadhyay, Sudipta email: sudiptachat@yahoo.com organization: Dept. of Electron. & Telecommun. Eng., Jadavpur Univ., Kolkata, India |
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| Snippet | Vedic mathematics is a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras or formulae. This technique is... |
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| SubjectTerms | 16 nm technology 65 nm technology Adders Algorithm design and analysis Delays Image coding McCMOS technology Simulation Urdhva Tiryakbhyam sutra Vedic multiplier |
| Title | Design of high performance 8 bit binary multiplier using vedic multiplication algorithm with 16 nm technology |
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