Dey, K., & Chattopadhyay, S. (2017, April). Design of high performance 8 bit binary multiplier using vedic multiplication algorithm with 16 nm technology. 2017 1st International Conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech), 1-5. https://doi.org/10.1109/IEMENTECH.2017.8076956
Citace podle Chicago (17th ed.)Dey, Koyel, a Sudipta Chattopadhyay. "Design of High Performance 8 Bit Binary Multiplier Using Vedic Multiplication Algorithm with 16 Nm Technology." 2017 1st International Conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech) Apr. 2017: 1-5. https://doi.org/10.1109/IEMENTECH.2017.8076956.
Citace podle MLA (9th ed.)Dey, Koyel, a Sudipta Chattopadhyay. "Design of High Performance 8 Bit Binary Multiplier Using Vedic Multiplication Algorithm with 16 Nm Technology." 2017 1st International Conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech), Apr. 2017, pp. 1-5, https://doi.org/10.1109/IEMENTECH.2017.8076956.