Flexible FPGA implementation of Min-Sum decoding algorithm for regular LDPC codes

Because of their excellent error correction performance, Low-Density Parity Check Codes (LDPC) have become the most widely used technique for forward error correction in almost all modern communications applications. This paper introduces an FPGA implementation of a partial parallel, flexible LDPC d...

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Bibliographic Details

Published in:	2016 11th International Conference on Computer Engineering & Systems (ICCES) pp. 286 - 292
Main Authors:	Sadek, Ahmed M., Hussein, Aziza I.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.12.2016
Subjects:	Approximation algorithms Complexity theory Decoding FEC Field programmable gate arrays FPGA implementation iterative decoding LDPC minimum sum algorithm Parity check codes partial parallel decoder permutation networks Introduction Program processors Random access memory
Online Access:	Get full text
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