Sadek, A. M., & Hussein, A. I. (2016, December). Flexible FPGA implementation of Min-Sum decoding algorithm for regular LDPC codes. 2016 11th International Conference on Computer Engineering & Systems (ICCES), 286-292. https://doi.org/10.1109/ICCES.2016.7822016
Chicago-Zitierstil (17. Ausg.)Sadek, Ahmed M., und Aziza I. Hussein. "Flexible FPGA Implementation of Min-Sum Decoding Algorithm for Regular LDPC Codes." 2016 11th International Conference on Computer Engineering & Systems (ICCES) Dec. 2016: 286-292. https://doi.org/10.1109/ICCES.2016.7822016.
MLA-Zitierstil (9. Ausg.)Sadek, Ahmed M., und Aziza I. Hussein. "Flexible FPGA Implementation of Min-Sum Decoding Algorithm for Regular LDPC Codes." 2016 11th International Conference on Computer Engineering & Systems (ICCES), Dec. 2016, pp. 286-292, https://doi.org/10.1109/ICCES.2016.7822016.