HEVC video encoder & decoder architecture for multi-cores

HEVC is the latest generation of video compression standard promising half bit-rate compared H.264 and enabling transition to 4K/Ultra-HD. The approach of designing a single monolithic engine for Ultra-HD resolution results in complex design due to very deep pipeline as well as non-optimal solution...

Full description

Saved in:
Bibliographic Details
Published in:Signal Processing and Communications Applications Conference pp. 1 - 5
Main Author: Mody, Mihir
Format: Conference Proceeding
Language:English
Published: IEEE 01.07.2014
Subjects:
Decoder
Decoding
Encoder
Filtering
H.265
HEVC
IP networks
Loop filter
Multi-core
Multicore processing
Multiple HW instances
Pipelines
Scalable
Strips
Video
ISSN:2165-0608
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:HEVC is the latest generation of video compression standard promising half bit-rate compared H.264 and enabling transition to 4K/Ultra-HD. The approach of designing a single monolithic engine for Ultra-HD resolution results in complex design due to very deep pipeline as well as non-optimal solution for lower resolution e.g HD or lower. The alternative approach for performance up-scaling using multiple copies of HW engines and/or processor cores has issues in partitioning video frame across these cores due to loop-filtering dependencies across slice and tiles. The prior approaches handling dependencies via disabling loop filtering or degrading video quality or additional frame latencies have un-acceptable disadvantages. This paper proposes a novel solution consisting of algorithmic and implementation ideas to address these limitations. The paper introduces usage of vertical tile strips, customized loop-filter architecture, sharing dependencies across these cores, intelligent scheduling of cores resulting in row synchronous pipeline across cores. The solution is applicable to HEVC encoder as well as decoder. The simulations shows that overall 4X performance lift using 4 processing cores or HW engines with less than 15% additional clocking requirement.
ISSN:2165-0608
DOI:10.1109/SPCOM.2014.6983918