Powerful LDPC Codes for Broadband Wireless Networks: High-performance Code Construction and High-speed Encoder/Decoder Design

This paper discusses high-performance code construction and high-speed encoder and decoder designs for low density parity check (LDPC) codes. Thanks to their nice structures, LDPC codes constructed from shifted identity matrices have been emphasized. Several techniques in code constructions have bee...

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Vydáno v:2007 International Symposium on Signals, Systems and Electronics s. 173 - 176
Hlavní autoři: Zhiyong He, Roy, S., Fortier, P.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.07.2007
Témata:
Bit error rate
Code standards
Digital video broadcasting
Encoding
Field programmable gate arrays
Floors
Iterative decoding
Parity check codes
Throughput
Wireless networks
ISBN:1424414482, 9781424414482
ISSN:2161-0819
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Shrnutí:This paper discusses high-performance code construction and high-speed encoder and decoder designs for low density parity check (LDPC) codes. Thanks to their nice structures, LDPC codes constructed from shifted identity matrices have been emphasized. Several techniques in code constructions have been proposed to lower the bit error floor down to 10 -10 . Characterized by a parity check matrix in a triangular plus dual-diagonal form, these structured LDPC codes can be encoded in linear time using a layered encoding algorithm. To increase the throughput of decoders, a joint row-column decoding algorithm has been proposed and parallel decoding architectures have been used. The implementation results into field programmable gate array (FPGA) devices indicate that the encoder for these high-performance LDPC codes attains a throughput of up to 115 Gbits/sec and the decoder attains a throughput of up to 1 Gbits/sec. The proposed codes are suitable for high-speed and high-performance applications which demand relatively low error floor, including application in broadband wireless networks.
ISBN:1424414482
9781424414482
ISSN:2161-0819
DOI:10.1109/ISSSE.2007.4294441