L2 Cache Modeling for Scientific Applications on Chip Multi-Processors

It is critical to provide high performance for scientific applications running on chip multi-processors (CMP). A CMP architecture often comprises a shared 12 cache and lower-level storages. The shared 12 cache can reduce the number of cache misses if the data are accessed in common by several thread...

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Veröffentlicht in:	Proceedings of the International Conference on Parallel Processing S. 51
Hauptverfasser:	Fengguang Song, Moore, S., Dongarra, J.
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 01.09.2007
Schlagworte:	Analytical models Application software architecture cache Capacity planning chip multi-processor Computer architecture Computer science Degradation multi-threaded programming Parallel processing performance modeling Predictive models Sparse matrices Yarn
ISSN:	0190-3918
Online-Zugang:	Volltext
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