FPGA implementation and verification of LDPC minimum sum algorithm decoder with weight (3, 6) regular parity check matrix

This work uses a regular parity check matrix with weight (3, 6) on the 5641R plate card of the Software-Defined Radio (SDR) system developed by National Instruments. The Min-Sum Algorithm (MSA) decoder of the Low Density Parity Check (LDPC) codes is completed using the LabVIEW FPGA. Subsequently, in...

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Bibliographic Details

Published in:	2013 IEEE 11th International Conference on Electronic Measurement and Instruments (ICEMI) Vol. 2; pp. 682 - 686
Main Authors:	Yi-Hua Chen, Chang-Lueng Chu, Jheng-Shyuan He
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.08.2013
Subjects:	approximate lower triangular Arrays Channel coding Decoding Field programmable gate arrays Iterative decoding LDPC MSA SDR
ISBN:	147990757X, 9781479907571
Online Access:	Get full text
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