FPGA implementation and verification of LDPC minimum sum algorithm decoder with weight (3, 6) regular parity check matrix

This work uses a regular parity check matrix with weight (3, 6) on the 5641R plate card of the Software-Defined Radio (SDR) system developed by National Instruments. The Min-Sum Algorithm (MSA) decoder of the Low Density Parity Check (LDPC) codes is completed using the LabVIEW FPGA. Subsequently, in...

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Veröffentlicht in:2013 IEEE 11th International Conference on Electronic Measurement and Instruments (ICEMI) Jg. 2; S. 682 - 686
Hauptverfasser: Yi-Hua Chen, Chang-Lueng Chu, Jheng-Shyuan He
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.08.2013
Schlagworte:
approximate lower triangular
Arrays
Channel coding
Decoding
Field programmable gate arrays
Iterative decoding
LDPC
MSA
SDR
ISBN:147990757X, 9781479907571
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Zusammenfassung:This work uses a regular parity check matrix with weight (3, 6) on the 5641R plate card of the Software-Defined Radio (SDR) system developed by National Instruments. The Min-Sum Algorithm (MSA) decoder of the Low Density Parity Check (LDPC) codes is completed using the LabVIEW FPGA. Subsequently, integration with the approximate lower triangular LDPC codes complement the complete LDPC encoding and decoding system. In addition to an explicit description of the decoding mechanism of the LDPC-code MSA decoder, analyses of decoding program optimization efficiency and Bit Error Rate (BER) performance curves are conducted. The program simulation results of FPGA indicate that under the additive white Gaussian noise environment, if the BER is 1 E-05, the Signal-to-Noise Ratio (SNR) without using LDPC code is 9.6 dB. The SNR of the LDPC MSA decoder with a min-sum one iteration and ten iterations are 6.8 dB and 6 dB, respectively; the coding gain of the MSA decoder with min-sum one iteration and 10 iterations is 2.8 dB and 3.6 dB, respectively, showing a discrepancy of 0.8 dB.
ISBN:147990757X
9781479907571
DOI:10.1109/ICEMI.2013.6743140