Chen, Y., Chu, C., & He, J. (2013). FPGA implementation and verification of LDPC minimum sum algorithm decoder with weight (3, 6) regular parity check matrix. 2013 IEEE 11th International Conference on Electronic Measurement and Instruments (ICEMI), 2, 682-686. https://doi.org/10.1109/ICEMI.2013.6743140
Citace podle Chicago (17th ed.)Chen, Yi-Hua, Chang-Lueng Chu, a Jheng-Shyuan He. "FPGA Implementation and Verification of LDPC Minimum Sum Algorithm Decoder with Weight (3, 6) Regular Parity Check Matrix." 2013 IEEE 11th International Conference on Electronic Measurement and Instruments (ICEMI) 2 (2013): 682-686. https://doi.org/10.1109/ICEMI.2013.6743140.
Citace podle MLA (9th ed.)Chen, Yi-Hua, et al. "FPGA Implementation and Verification of LDPC Minimum Sum Algorithm Decoder with Weight (3, 6) Regular Parity Check Matrix." 2013 IEEE 11th International Conference on Electronic Measurement and Instruments (ICEMI), vol. 2, 2013, pp. 682-686, https://doi.org/10.1109/ICEMI.2013.6743140.