An efficient methodology for transaction-level design of multi-core h.264 video decoder
H.264 video decoder is a good choice for embedded instruments because of its higher compression ratio than MPEG2, as well as its higher requirements of run-time computational resource. Multi-core system is the future of the embedded processor design for its power efficiency and multi-thread parallel...
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| Vydáno v: | 2011 IEEE International Conference on Consumer Electronics (ICCE) s. 399 - 400 |
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| Hlavní autoři: | , , , |
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| Jazyk: | angličtina |
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IEEE
01.01.2011
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| ISBN: | 9781424487110, 1424487110 |
| ISSN: | 2158-3994 |
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| Abstract | H.264 video decoder is a good choice for embedded instruments because of its higher compression ratio than MPEG2, as well as its higher requirements of run-time computational resource. Multi-core system is the future of the embedded processor design for its power efficiency and multi-thread parallelization, and can be used to fit well with the requirements for this decoder. To simulate and evaluate the performance of such application-specific multi-core systems effectively, a method based on the combination of TLM language (SystemC) and shared-memory parallel programming model (OpenMP) is given, and experiments show that it can effectively simulate the system in a short time and more importantly, it can be used to help analyze the efficiency of each task-parallelization strategy. After optimization, the speedup ratio for each slice decoding can get about 3.06 on average under 4-core multi-core systems. |
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| AbstractList | H.264 video decoder is a good choice for embedded instruments because of its higher compression ratio than MPEG2, as well as its higher requirements of run-time computational resource. Multi-core system is the future of the embedded processor design for its power efficiency and multi-thread parallelization, and can be used to fit well with the requirements for this decoder. To simulate and evaluate the performance of such application-specific multi-core systems effectively, a method based on the combination of TLM language (SystemC) and shared-memory parallel programming model (OpenMP) is given, and experiments show that it can effectively simulate the system in a short time and more importantly, it can be used to help analyze the efficiency of each task-parallelization strategy. After optimization, the speedup ratio for each slice decoding can get about 3.06 on average under 4-core multi-core systems. |
| Author | Fei Qiao Hui Wang Bingbing Xia Huazhong Yang |
| Author_xml | – sequence: 1 surname: Bingbing Xia fullname: Bingbing Xia email: xbb07@mails.tsinghua.edu.cn organization: Tsinghua Nat. Lab. for Inf. & Technol., Tsinghua Univ., Beijing, China – sequence: 2 surname: Fei Qiao fullname: Fei Qiao organization: Tsinghua Nat. Lab. for Inf. & Technol., Tsinghua Univ., Beijing, China – sequence: 3 surname: Huazhong Yang fullname: Huazhong Yang organization: Tsinghua Nat. Lab. for Inf. & Technol., Tsinghua Univ., Beijing, China – sequence: 4 surname: Hui Wang fullname: Hui Wang organization: Tsinghua Nat. Lab. for Inf. & Technol., Tsinghua Univ., Beijing, China |
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| Snippet | H.264 video decoder is a good choice for embedded instruments because of its higher compression ratio than MPEG2, as well as its higher requirements of... |
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| SubjectTerms | Analytical models Decoding Design methodology Multicore processing Parallel programming Time domain analysis Time varying systems |
| Title | An efficient methodology for transaction-level design of multi-core h.264 video decoder |
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