A parallel architecture for data compression

The authors describe a parallel algorithm and architecture for implementing the LZ technique for data compression. Data compression is the reduction of redundancy in data representation in order to decrease storage and communication costs. The LZ-based compression method is a very powerful technique...

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Bibliographic Details
Published in:Parallel and Distributed Processing, 2nd IEEE Symposium On pp. 260 - 266
Main Authors: Henriques, S., Ranganathan, N.
Format: Conference Proceeding
Language:English
Published: IEEE Comput. Soc. Press 1990
Subjects:
CMOS technology
Computer architecture
Costs
Data compression
Image coding
Parallel algorithms
Parallel architectures
Parallel processing
Pipeline processing
Throughput
ISBN:0818620870, 9780818620874
Online Access:Get full text
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Summary:The authors describe a parallel algorithm and architecture for implementing the LZ technique for data compression. Data compression is the reduction of redundancy in data representation in order to decrease storage and communication costs. The LZ-based compression method is a very powerful technique and gives very high compression efficiency for text as well as image data. The proposed architecture is systolic and uses the principles of pipelining and parallelism in order to obtain high speed and throughput. The order of complexity of the computations is reduced from n/sup 2/ to n. The data compression hardware can be integrated into real time systems so that data can be compressed and decompressed on-the-fly. The basic processor cell for the systolic array is currently being implemented using CMOS VLSI technology.< >
ISBN:0818620870
9780818620874
DOI:10.1109/SPDP.1990.143545