A novel VHDL-based computer architecture design methodology

There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The single path design methodology presented is a possible solution to this problem. The basic concept of the methodology is the use of one simulati...

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Vydáno v:Rapid System Prototyping, 3rd International Workshop (RSP '92) s. 292 - 300
Hlavní autoři: MacDonald, R., Srinivasan, S., Williams, R., Aylor, J.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE Comput. Soc. Press 1992
Témata:
Circuit simulation
Computational modeling
Computer architecture
Design automation
Design methodology
Digital systems
Performance analysis
Petri nets
Process design
Queueing analysis
ISBN:0818635207, 9780818635205
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Abstract There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The single path design methodology presented is a possible solution to this problem. The basic concept of the methodology is the use of one simulation language, the VHSIC hardware description language (VHDL, Version 1076) for all phases of design. The VHDL framework allows for iterative stepwise refinement of a model. A performance (uninterpreted) model can be refined to a register transfer level (RTL) description without changing modeling environments or completely rewriting the models. As an example, the performance-modeling phase of the single path design methodology is applied to the WM machine, a superscalar computer architecture.< >
AbstractList There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The single path design methodology presented is a possible solution to this problem. The basic concept of the methodology is the use of one simulation language, the VHSIC hardware description language (VHDL, Version 1076) for all phases of design. The VHDL framework allows for iterative stepwise refinement of a model. A performance (uninterpreted) model can be refined to a register transfer level (RTL) description without changing modeling environments or completely rewriting the models. As an example, the performance-modeling phase of the single path design methodology is applied to the WM machine, a superscalar computer architecture.< >
Author Williams, R.
MacDonald, R.
Srinivasan, S.
Aylor, J.
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  organization: Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
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PublicationTitle Rapid System Prototyping, 3rd International Workshop (RSP '92)
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Snippet There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The...
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StartPage 292
SubjectTerms Circuit simulation
Computational modeling
Computer architecture
Design automation
Design methodology
Digital systems
Performance analysis
Petri nets
Process design
Queueing analysis
Title A novel VHDL-based computer architecture design methodology
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