Stream-interleaved pipelined RISC processor design for SIMD and MIMD system development
Architectures exploiting time and space parallelism can be used to increase performance. Reduced instruction set computers (RISC) enhance performance of a single instruction stream through a simple load/store architecture. Data dependencies are eliminated by introducing NOP instructions in the strea...
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| Vydáno v: | 1993 (25th) Southeastern Symposium on System Theory s. 452 - 456 |
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| Hlavní autoři: | , |
| Médium: | Konferenční příspěvek |
| Jazyk: | angličtina |
| Vydáno: |
IEEE
1993
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| Témata: | |
| ISBN: | 0818635606, 9780818635601 |
| ISSN: | 0094-2898 |
| On-line přístup: | Získat plný text |
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| Abstract | Architectures exploiting time and space parallelism can be used to increase performance. Reduced instruction set computers (RISC) enhance performance of a single instruction stream through a simple load/store architecture. Data dependencies are eliminated by introducing NOP instructions in the stream. A longer pipeline increases the proportion of NOPs. These gaps may be used to interleave multiple instruction streams. A typical parallel organization based on message passing via main memory undermines the efficiency of a load/store architecture. The authors propose a method of sharing internal registers between instruction streams, forming a building block for efficient SIMD and MIMD systems. |
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| AbstractList | Architectures exploiting time and space parallelism can be used to increase performance. Reduced instruction set computers (RISC) enhance performance of a single instruction stream through a simple load/store architecture. Data dependencies are eliminated by introducing NOP instructions in the stream. A longer pipeline increases the proportion of NOPs. These gaps may be used to interleave multiple instruction streams. A typical parallel organization based on message passing via main memory undermines the efficiency of a load/store architecture. The authors propose a method of sharing internal registers between instruction streams, forming a building block for efficient SIMD and MIMD systems. |
| Author | Killeen, T. Celenk, M. |
| Author_xml | – sequence: 1 givenname: T. surname: Killeen fullname: Killeen, T. organization: Dept. of Electr. & Comput. Eng., Ohio Univ., Athens, OH, USA – sequence: 2 givenname: M. surname: Celenk fullname: Celenk, M. organization: Dept. of Electr. & Comput. Eng., Ohio Univ., Athens, OH, USA |
| BookMark | eNot0F1LwzAYBeCAE9ym9-JV_0Drm6ZJm0upX4UNwRa8HFnyRiJtWpIy2L-3Mq_OAwfOxdmQlR89EnJPIaMU5GPbtl1GpWQZz_Mqp1dkAxWtBOMCxIqsAWSR5pWsbsgmxh8AECLna_LVzgHVkDo_Y-hRndAkk5uwd37RZ9PWyRRGjTGOITEY3bdP7MK22T8nyptk_4d4jjMOS3_CfpwG9PMtubaqj3j3n1vSvb509Xu6-3hr6qdd6io5p5IyKJTWiqOSZckBIYejtVogk6XR5sg1UC5sKSgKURRaGaMoE9pyo0vFtuThMusQ8TAFN6hwPlwuYL9y4lLj |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IL CBEJK RIE RIL |
| DOI | 10.1109/SSST.1993.522821 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings Accès Toulouse INP et ENVT - IEEE Xplore POP ALL IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP All) 1998-Present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EndPage | 456 |
| ExternalDocumentID | 522821 |
| GroupedDBID | -~X 29O 29Q 6IE 6IF 6IH 6IK 6IL 6IM 6IN AAJGR AAWTH ACGFS ADZIZ AFFNX ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO IEGSK IJVOP IPLJI M43 OCL RIE RIL RNS |
| ID | FETCH-LOGICAL-i89t-91304acca5ea97750e020bffc6e397dcdb5c0156f761e6644cadda136cf5dc7a3 |
| IEDL.DBID | RIE |
| ISBN | 0818635606 9780818635601 |
| ISSN | 0094-2898 |
| IngestDate | Tue Aug 26 22:26:30 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-i89t-91304acca5ea97750e020bffc6e397dcdb5c0156f761e6644cadda136cf5dc7a3 |
| PageCount | 5 |
| ParticipantIDs | ieee_primary_522821 |
| PublicationCentury | 1900 |
| PublicationDate | 19930000 |
| PublicationDateYYYYMMDD | 1993-01-01 |
| PublicationDate_xml | – year: 1993 text: 19930000 |
| PublicationDecade | 1990 |
| PublicationTitle | 1993 (25th) Southeastern Symposium on System Theory |
| PublicationTitleAbbrev | SSST |
| PublicationYear | 1993 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| SSID | ssj0006625 ssj0000434295 |
| Score | 1.3261973 |
| Snippet | Architectures exploiting time and space parallelism can be used to increase performance. Reduced instruction set computers (RISC) enhance performance of a... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 452 |
| SubjectTerms | Computer aided instruction Computer architecture Interleaved codes Multitasking Parallel processing Pipeline processing Process design Reduced instruction set computing Registers Very large scale integration |
| Title | Stream-interleaved pipelined RISC processor design for SIMD and MIMD system development |
| URI | https://ieeexplore.ieee.org/document/522821 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlZ3PS8MwFMeDDg96UefE3-TgNVvTtGl7ng4Hbgw7cLeRJi8w0K7Ubn-_-bEfCl68paXQkkDy7Xvv-3kIPVKpGTAORGuuSJSEkqRaM6IDrgrBg1AJh8x_TcbjdDbLJhvOtvPCAIArPoOuHbpcvlrKlQ2V9YxWSK1p_DBJuLdq7cIpQcSiMNsrX85D37wgi4j5p0gd-pGmlsYW8A14Z3tNt-nLIOvleT61Dj7W9S_71XTFnTmD03997Rnq7L17eLI7lc7RAZRtdPIDO3iB3m0qWnwSi4qoP0CsQeFqUVlnuhm9DfM-rrx_YFlj5Uo8sNG2OB-OnrAoFR7ZgWdAY7WvOuqg6eB52n8hmwYLZJFmjU26B5EwSxiDMDIwDsBox0JrycGoFCVVEUvrtNYJp8CNcJJmMxSUcaljJRPBLlGrXJZwhTCPlTaPsYgVNKIgU4u9ByozCWZTkPoate0EzSuP0Jj7ubn58-4tOvZVhTbOcYdaTb2Ce3Qk183iq35wy_4NF5SoXg |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlZ3PS8MwFMeDTEG9qHPib3Pwmi1t0rQ9T2XDbQxbcLeRJi8w0K7UbX-_SbsfCl68vZZCS1qSb_Pe9_MQevSUYcAEEGOEJjz0FYmMYcRQoTMpqK9lhcwfhKNRNJnE4zVnu_LCAEBVfAZtF1a5fD1XS7dV1rFaIXKm8f2Ac5_WZq3thgrljPvxTvsK4dftC2JO7F9FVMEfvcjx2KhYo3c2x94mgUnjTpIkqfPwsXZ9u19tV6pV5-XkX897ilo79x4eb9elM7QHeRMd_wAPnqN3l4yWn8TBIsoPkCvQuJgVzptuo7d-0sVF7SCYl1hXRR7Yqluc9IdPWOYaD11QU6Cx3tUdtVD68px2e2TdYoHMonjh0u6US_sSA5BWCAYUrHrMjFECrE7RSmeBcl5rEwoPhJVOyk6H0mNCmUCrULIL1MjnOVwiLAJt7GWMs8zjHqjIge_BU7ECOy0oc4WaboCmRQ3RmNZjc_3n2Qd02EuHg-mgP3q9QUd1jaHb9bhFjUW5hDt0oFaL2Vd5X30C3w3-q6U |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=1993+%2825th%29+Southeastern+Symposium+on+System+Theory&rft.atitle=Stream-interleaved+pipelined+RISC+processor+design+for+SIMD+and+MIMD+system+development&rft.au=Killeen%2C+T.&rft.au=Celenk%2C+M.&rft.date=1993-01-01&rft.pub=IEEE&rft.isbn=9780818635601&rft.issn=0094-2898&rft.spage=452&rft.epage=456&rft_id=info:doi/10.1109%2FSSST.1993.522821&rft.externalDocID=522821 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0094-2898&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0094-2898&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0094-2898&client=summon |