Irregular rate-compatible LDPC codes for capacity-approaching hybrid-ARQ schemes - Yazdani, M.; Banihashemi, A.H. (Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513), 2004)
In this paper, we describe the construction method of a family of irregular rate-compatible low-density parity-check (LDPC) codes by a combination of puncturing and extending techniques. In particular, we introduce a suitable structure for the extended parity-check matrices which preserves the structure of LDPC codes during extensions. Based on this construction, a family of efficient rate-compatible linear-time encodable codes are generated from an optimized irregular mother code of rate 8/13 and information block length k=1024. The rates of the codes vary from 8/10 to 8/19 and employing them in a type-II hybrid ARQ scheme results in a throughput which is only 0.7 dB away from the Shannon limit. This improves over the existing schemes, based on turbo codes and LDPC codes, by up to 0.5 dB.