Parallel-and-vector implementation of the event-driven logic simulation algorithm on the Cray Y-MP supercomputer

The authors propose logic simulation techniques using parallel and vector machines to reduce the simulation time of large digital circuits. Three algorithms for logic simulation have been developed and implemented on the Cray Y-MP supercomputer, a general-purpose shared-memory parallel machine with...

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Vydané v:	Supercomputing, `92 s. 444 - 452
Hlavní autori:	Bataineh, A., Ozguner, F.
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE Comput. Soc. Press 1992
Predmet:	Circuit simulation Clocks Computational modeling Concurrent computing Digital circuits Discrete event simulation Hardware Logic circuits Logic design Supercomputers
ISBN:	9780818626302, 0818626305
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