Assertion based verification using HDVL

Over the past several years verification of large designs are becoming more and more complex-both in terms of the maintaining the code size and in keeping parity between the specification written in English; design written in HDL (typically Verilog/VHDL) and the verification models-written in HDL or...

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Bibliographische Detailangaben
Veröffentlicht in:	Proceedings /17th International Conference on VLSI Design, concurrently with the 3rd International Conference on Embedded Systems Design, 5-9 January, 2004, Mumbai, India S. 319 - 325
Hauptverfasser:	Datta, K., Das, P.P.
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	Los Alamitos CA IEEE 2004 IEEE Computer Society
Schlagworte:	Applied sciences Computer bugs Design engineering Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Formal languages Formal verification Hardware design languages Integrated circuits Natural languages Power engineering and energy Proposals Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sugar industry System testing Integrated circuit design Hardware description languages VLSI circuit Review Coding VHDL language
ISBN:	0769520723, 9780769520728
Online-Zugang:	Volltext
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