Real-time low-energy fall detection algorithm with a Programmable Truncated MAC

The ability to discriminate between falls and activities of daily living (ADL) has been investigated by using tri-axial accelerometer sensors, mounted on the trunk and using simulated falls performed by young healthy subjects under supervised conditions and ADL performed by elderly subjects. In this...

Full description

Saved in:
Bibliographic Details
Published in:2010 Annual International Conference of the IEEE Engineering in Medicine and Biology Vol. 2010; pp. 2423 - 2426
Main Authors: de la Guia Solaz, Manuel, Bourke, Alan, Conway, Richard, Nelson, John, ÓLaighin, Gearóid
Format: Conference Proceeding Journal Article
Language:English
Published: United States IEEE 01.01.2010
Subjects:
Accelerometers
Accidental Falls - prevention & control
Accuracy
Activities of Daily Living
Adult
Algorithms
Computer Simulation
Computers
Detection algorithms
Digital signal processing
Humans
Monitoring, Ambulatory - instrumentation
Monitoring, Ambulatory - methods
Movement
Postural Balance
Posture
Real time systems
Reproducibility of Results
Senior citizens
Sensors
Software
ISBN:1424441234, 9781424441235
ISSN:1094-687X, 1557-170X, 2375-7477
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The ability to discriminate between falls and activities of daily living (ADL) has been investigated by using tri-axial accelerometer sensors, mounted on the trunk and using simulated falls performed by young healthy subjects under supervised conditions and ADL performed by elderly subjects. In this paper we propose a power-aware real-time fall detection integrated circuit (IC) that can distinguish Falls from ADL by processing the accelerations measured during 240 falls and 240 ADL. In the proposed fixed point custom DSP architecture, a threshold algorithm was implemented to analyze the effectiveness of Programmable Truncated Multiplication regarding power reduction while maintaining a high output accuracy. The presented system runs a real time implementation of the algorithm on a low power architecture that allows up to 23% power savings through its digital blocks when compared to a standard implementation, without any accuracy loss.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISBN:1424441234
9781424441235
ISSN:1094-687X
1557-170X
2375-7477
DOI:10.1109/IEMBS.2010.5626244