Qubit placement to minimize communication overhead in 2D quantum architectures
Regular, local-neighbor topologies of quantum architectures restrict interactions to adjacent qubits, which in turn increases the latency of quantum circuits mapped to these architectures. To alleviate this effect, optimization methods that consider qubit-to-qubit interactions in 2D grid architectur...
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| Published in: | Proceedings of the ASP-DAC ... Asia and South Pacific Design Automation Conference pp. 495 - 500 |
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| Main Authors: | , , |
| Format: | Conference Proceeding |
| Language: | English |
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IEEE
01.01.2014
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| ISSN: | 2153-6961 |
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| Abstract | Regular, local-neighbor topologies of quantum architectures restrict interactions to adjacent qubits, which in turn increases the latency of quantum circuits mapped to these architectures. To alleviate this effect, optimization methods that consider qubit-to-qubit interactions in 2D grid architectures are presented in this paper. The proposed approaches benefit from Mixed Integer Programming (MIP) formulation for the qubit placement problem. Simulation results on various benchmarks show 27% on average reduction in communication overhead between qubits compared to best results of previous work. |
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| AbstractList | Regular, local-neighbor topologies of quantum architectures restrict interactions to adjacent qubits, which in turn increases the latency of quantum circuits mapped to these architectures. To alleviate this effect, optimization methods that consider qubit-to-qubit interactions in 2D grid architectures are presented in this paper. The proposed approaches benefit from Mixed Integer Programming (MIP) formulation for the qubit placement problem. Simulation results on various benchmarks show 27% on average reduction in communication overhead between qubits compared to best results of previous work. |
| Author | Saeedi, Mehdi Shafaei, Alireza Pedram, Massoud |
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| Snippet | Regular, local-neighbor topologies of quantum architectures restrict interactions to adjacent qubits, which in turn increases the latency of quantum circuits... |
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| SubjectTerms | Benchmark testing Computer architecture Linear programming Logic gates Optimization Quantum computing Very large scale integration |
| Title | Qubit placement to minimize communication overhead in 2D quantum architectures |
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