The Random Address Shift to Reduce the Memory Access Congestion on the Discrete Memory Machine

The Discrete Memory Machine (DMM) is a theoretical parallel computing model that captures the essence of memory access of the streaming multiprocessor on CUDA-enabled GPUs. The DMM has w memory banks that constitute a shared memory, and w threads in a warp try to access them at the same time. Howeve...

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Veröffentlicht in:	International Symposium on Computing and Networking (Online) S. 95 - 103
Hauptverfasser:	Nakano, Koji, Matsumae, Susumu, Ito, Yasuaki
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 01.12.2013
Schlagworte:	Computational modeling CUDA GPU Graphics processing units Instruction sets memory access congestion memory bank conflicts Memory management Phase change random access memory Pipelines randomized technique Writing
ISSN:	2379-1888
Online-Zugang:	Volltext
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