Complete activation scheme for FPGA-oriented IP cores design protection

Intellectual Property (IP) illegal copying is a major threat in today's integrated circuits industry which is massively based on a design-and-reuse paradigm. In order to fight this threat, a designer must track how many times an IP has been instantiated. Moreover, illegal copies of an IP must b...

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Bibliographic Details
Published in:International Conference on Field-programmable Logic and Applications p. 1
Main Authors: Colombier, Brice, Mureddu, Ugo, Laban, Marek, Petura, Oto, Bossuet, Lilian, Fischer, Viktor
Format: Conference Proceeding
Language:English
Japanese
Published: Ghent University 01.09.2017
Subjects:
Cryptography
Europe
Hardware
IP networks
Multimedia communication
Software
User interfaces
ISSN:1946-1488
Online Access:Get full text
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Summary:Intellectual Property (IP) illegal copying is a major threat in today's integrated circuits industry which is massively based on a design-and-reuse paradigm. In order to fight this threat, a designer must track how many times an IP has been instantiated. Moreover, illegal copies of an IP must be unusable. We propose a hardware/software scheme which allows a designer to remotely activate an IP with minimal area overhead. The software modifies the IP efficiently and can handle very large netlists. Unique identification of hardware instances is achieved by integrating a TERO-PUF along with a lightweight key reconciliation module. A cryptographic core guarantees security and triggers a logic locking/masking module which makes the IP unusable unless the correct encrypted activation word is applied.
ISSN:1946-1488
DOI:10.23919/FPL.2017.8056772