Nested Pipeline Hardware Self-Organizing Map for High Dimensional Vectors

This paper proposes a hardware Self-Organizing Map (SOM) for high dimensional vectors. The proposed SOM is based on nested architecture with pipeline processing. Due to homogeneous modular structure, the nested architecture provides high expandability. The original nested SOM was designed to handle...

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Veröffentlicht in:	2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) S. 1 - 4
1. Verfasser:	Hikawa, Hiroomi
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 23.11.2020
Schlagworte:	Clocks clustering Computer architecture Field programmable gate arrays FPGA Hardware MNIST Neurons Pipelines Self-organizing feature maps Self-organizing map VHDL
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