Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures

Edge detection is a fundamental operation in image processing, serving as a crucial step in various applications such as object recognition, image segmentation, and scene understanding. The Sobel edge detection algorithm has emerged as a widely used method for detecting vertical and horizontal edges...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	Proceedings (Euromicro Conference on Digital Systems Design) S. 16 - 23
Hauptverfasser:	Pudi, Dhilleswararao, Ryansh, Rajeev, Goudu, Vamsi, Boppu, Srinivas, Hemani, Ahmed
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 06.09.2023
Schlagworte:	Coarse-grained reconfigurable array Distributed memory architecture Dynamically reconfigurable resource array Field programmable gate array Heuristic algorithms Image edge detection Laplace equations Logic gates Memory architecture Program processors Sobel edge detection
ISSN:	2771-2508
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	Edge detection is a fundamental operation in image processing, serving as a crucial step in various applications such as object recognition, image segmentation, and scene understanding. The Sobel edge detection algorithm has emerged as a widely used method for detecting vertical and horizontal edges in digital images. However, performing edge detection on high-resolution images with large dimensions can be computationally intensive and time-consuming. Specialized hardware solutions such as Field Programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Arrays (CGRAs) offer significant advantages over general-purpose processors for implementing edge detection algorithms. This paper proposes algorithms for implementing the Sobel edge detection algorithm using two CGRA fabrics: dynamically reconfigurable resource array and distributed memory architecture. Furthermore, we discuss the implementation of Sobel edge detection on the target architecture for an input matrix of arbitrary size. Finally, the proposed approaches were compared with other CGRA-based implementations in terms of latency. The experimental results show that the proposed approaches exhibit significantly lower latency compared to other CGRA - based implempntations.
ISSN:	2771-2508
DOI:	10.1109/DSD60849.2023.00013