Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA

Despite its popularity, deploying Convolutional Neural Networks (CNNs) on a portable system is still challenging due to large data volume, intensive computation and frequent memory access. Although previous FPGA acceleration schemes generated by high-level synthesis tools (i.e., HLS, OpenCL) have al...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	International Conference on Field-programmable Logic and Applications S. 1 - 8
Hauptverfasser:	Yufei Ma, Suda, Naveen, Yu Cao, Jae-sun Seo, Vrudhula, Sarma
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	EPFL 01.08.2016
Schlagworte:	Acceleration Algorithm design and analysis Convolution Convolutional neural networks Field programmable gate arrays FPGA Hardware hardware acceleration Kernel Memory management
ISSN:	1946-1488
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!