Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA

Despite its popularity, deploying Convolutional Neural Networks (CNNs) on a portable system is still challenging due to large data volume, intensive computation and frequent memory access. Although previous FPGA acceleration schemes generated by high-level synthesis tools (i.e., HLS, OpenCL) have al...

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Vydané v:	International Conference on Field-programmable Logic and Applications s. 1 - 8
Hlavní autori:	Yufei Ma, Suda, Naveen, Yu Cao, Jae-sun Seo, Vrudhula, Sarma
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	EPFL 01.08.2016
Predmet:	Acceleration Algorithm design and analysis Convolution Convolutional neural networks Field programmable gate arrays FPGA Hardware hardware acceleration Kernel Memory management
ISSN:	1946-1488
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